High yield sub-micron gate FETs

Details High yield sub-micron gate FETs High yield sub-micron gate FETs

1995-04-19

1996-07-23

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

257194, H01L 310328, H01L 310336, H01L 31072, H01L 31109

Patent

active

055392229

ABSTRACT:
Yields of FETs such as HEMTs are significantly improved by establishing an elongate gate contact opening in a patterning material with the patterning material overhanging the opening along both its elongate sides and its ends. A contact metal is next evaporated both into the opening and onto the adjacent patterning material, with the overhang producing a continuous gap around the periphery of the upper section of the gate contact between it and the metal on the adjacent patterning material. The adjacent metal is then lifted-off without disturbing the gate contact. The inward tapered profile in the elongate direction of the contact opening is achieved with multiple parallel e-beam scans, while a similar profile is achieved at the ends of the elongate scans by increasing the electron beam dose in the vicinity of the scan ends, preferably by scanning the beam at a substantial angle to the elongate direction near the ends of the opening.

REFERENCES:
patent: 4429452 (1984-02-01), Meignant
patent: 4882609 (1989-11-01), Schubert et al.
patent: 5028968 (1991-07-01), O'Loughlin et al.
patent: 5171718 (1992-12-01), Ishibashi et al.
patent: 5185277 (1993-02-01), Tung et al.
patent: 5190892 (1993-03-01), Sano
patent: 5336626 (1994-08-01), Lee

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