High yield processing for silicon-on-sapphire CMOS integrated ci

Details High yield processing for silicon-on-sapphire CMOS integrated ci High yield processing for silicon-on-sapphire CMOS integrated ci

1978-12-11

1980-01-15

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

148 15, 148187, 148188, 357 42, H01L 2122, H01L 2126

Patent

active

041831349

ABSTRACT:
Described herein a technique for constructing a complementary MOS device on a sapphire substrate so that the surface of the device is planarized, the P-channel and N-channel devices are in substantially correct registration, the threshold voltage for the back-channel leakage effect inherent in sapphire substrate device to occur is increased, and the areas of gate oxidation are pseudo self-aligned so as to minimize overlap of the gate oxide with the source and drain regions.

REFERENCES:
patent: 3442011 (1969-05-01), Strieter
patent: 3566518 (1971-03-01), Brown et al.
patent: 3657613 (1972-04-01), Brody et al.
patent: 3745072 (1973-07-01), Scott
patent: 3837071 (1974-09-01), Ronen
patent: 3865653 (1975-02-01), Goser
patent: 3909307 (1975-08-01), Stein
patent: 4023195 (1977-05-01), Richman
Dataquest Inc., "Silicon on Sapphire", Palo Alto, Calif., Feb. 21, 1975, pp. 37-59.

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