High yield plasma etch process for interlayer dielectrics

Details High yield plasma etch process for interlayer dielectrics High yield plasma etch process for interlayer dielectrics

2007-10-05

2011-11-22

Vinh, Lan (Department: 1713)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S714000, C438S740000, C438S744000

Reexamination Certificate

active

08062982

ABSTRACT:
A high yield plasma etch process for an interlayer dielectric layer of a semiconductor device is provided, according to an embodiment of which a dielectric layer is etched with a nitrogen-containing plasma. In this way, the formation of polymers on a backside bevel of a substrate is avoided or substantially reduced. Remaining polymer at the backside bevel can be removed in situ by post-etch treatment. Further, a plasma etching device is provided comprising a chamber, a substrate receiving space for receiving a substrate, a plasma generator for generating a plasma in the chamber and a temperature conditioner for conditioning a temperature at an outer circumferential region of the substrate receiving space and thereby minimizing temperature gradients at a bevel of the wafer.

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Thomson-Derwent Abstract from WPI-Online, found in STN, acc#2006-498273[51] KR20050067817 A.
German Office Communication dated Oct. 19, 2007.

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