Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1996-05-22
1997-07-01
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
257520, 257506, 257508, 257487, 257526, H01L 2973, H01L 2980, H01L 2706
Patent
active
056441576
ABSTRACT:
A semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. A PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14. This mitigates electrostatic focusing in the vicinity of the corner parts between the sides of the base region 5 and the bottom thereof, restraining the avalanche breakdown there and improving the withstand voltage there.
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Iida Makio
Ishihara Osamu
Miura Shoji
Sakakibara Toshio
Sugisaka Takayuki
Crane Sara W.
Nippondenso Co. Ltd.
Williams Alexander Oscar
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