High withstand voltage structure of a semiconductor integrated c

Details High withstand voltage structure of a semiconductor integrated c High withstand voltage structure of a semiconductor integrated c

1981-07-30

1984-10-09

Munson, Gene M.

357 48, 357 89, H01L 2702, H01L 2704

Patent

active

044764804

ABSTRACT:
A vertical PNP transistor having a large withstand voltage is disclosed. On a P-type substrate, a N-type epitaxial layer is provided. A P-type isolation region is formed in the epitaxial layer as a closed-loop to isolate a portion of the epitaxial layer from the other portions thereof. A first N-type buried layer is formed in the isolated epitaxial layer at the interface of the epitaxial layer and the semiconductor layer so as to separate the two. A second P-type buried layer is provided on top of the first buried layer. A P-type collector region is formed as a second closed-loop in the epitaxial layer enclosed within the first closed-loop. A high N-type concentration region that permits great withstand voltage is formed as a closed-loop separating the first closed-loop and the second closed-loop regions. A P-type emitter region is formed in the epitaxial layer region enclosed within the second closed-loop. Without the emitter region, the device can be used as a diode. By adding a N-type region within the emitter region, an NPNP thyristor can be obtained.

REFERENCES:
patent: 3648128 (1972-03-01), Kobayashi
patent: 3702428 (1972-11-01), Schmitz et al.
patent: 4038680 (1977-07-01), Yagi et al.
patent: 4087900 (1978-05-01), Yiannoulos
Chang et al. "Fabrication of PNP and NPN Transistors in a Single Wafer or Chip" IBM Tech. Disclosure Bulletin vol. 11 (5/69) pp. 1653-1654.

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