High votage latch using CMOS transistors and method therefor

Details High votage latch using CMOS transistors and method therefor High votage latch using CMOS transistors and method therefor

1997-01-10

1998-12-01

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

327208, 327210, H03K 3356

Patent

active

058444416

ABSTRACT:
A high voltage data latch with complementary outputs that are each set to one of two voltage levels (V.sub.pp and V.sub.b). The high voltage data latch is designed using CMOS technology wherein no PMOS transistors have a voltage level greater than V.sub.pp /2 volts across any node. This will allow PMOS transistors with lower voltage breakdown levels to be used. The high voltage data latch has two modes of operation. In a low voltage mode (V.sub.pp =V.sub.DD and V.sub.b =Ground) the outputs switch with respect to the inputs. In a high voltage mode (V.sub.pp >V.sub.b >V.sub.dd) the outputs will be latched to the state they were in when the voltage rails changed states from the low voltage mode to the high voltage mode.

REFERENCES:
patent: 4532436 (1985-07-01), Bicmark

Affiliated with

Also associated with

Rating

High votage latch using CMOS transistors and method therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High votage latch using CMOS transistors and method therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High votage latch using CMOS transistors and method therefor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2398613