High voltage transistor protection technique and switching...

Details High voltage transistor protection technique and switching... High voltage transistor protection technique and switching...

2003-02-07

2004-05-04

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C327S333000, C327S112000

Reexamination Certificate

active

06731156

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit (“IC”) devices. More particularly, the present invention relates to a high voltage transistor protection technique and switching circuit of especial applicability to integrated circuit devices utilizing multiple power supply voltages.
In certain integrated circuit devices (e.g. some memory ICs) a high voltage supply level (“V
PP
”) may be required for proper device operation. When V
PP
is less than to equal to twice the supply voltage (“V
CC
”), i.e. V
PP
≦2*V
CC
, then in certain technologies, a single protect transistor may be utilized in a switching circuit wherein the output must be switched between V
PP
and circuit ground (“GND” or “V
SS
”). The resultant structure is a series connected pair of relatively thin gate oxide MOS transistors coupled between the output node and V
SS
with the gate of the upper device coupled to V
CC
and the gate of the lower device defining an input node receiving a switched source of V
CC
.
In those applications wherein the high voltage supply level is more than twice the device supply voltage (“V
CC
”) i.e. V
PP
>2*V
CC
, then a switching circuit comprising a relatively thick gate oxide MOS transistor in series with a pair of series connected relatively thin gate oxide MOS transistors may be coupled between the output node and V
SS
with the gate of the thick gate oxide device coupled to a source of V
PP
, the gate of the intermediate N-channel device coupled to V
CC
and the gate of the remaining N-channel device coupled to an input node receiving a switched source of V
CC
.
In general, prior art switching circuits for use in devices requiring multiple voltage supply levels, particularly those wherein V
PP
>2*V
CC
, have required many transistors in series to convert voltage levels. This results in the consumption of a relatively large amount of on-chip die area for the layout of these circuits along with concomitant device speed degradation.
SUMMARY OF THE INVENTION
The high voltage transistor protection technique, of the present invention overcomes the problems inherent in the amount of on-chip die area consumed an d speed degradation of prior art circuit implementations and is of particular applicability to integrated circuit devices employing multiple power supply voltages.
Particularly disclosed herein is a switching circuit for operation in conjunction with a first supply voltage V
PP
and a second lower supply voltage V
CC
wherein V
PP
>2*V
CC
. The circuit comprises a first transistor having an input terminal thereof coupled between an output of the circuit and an intermediate node with the output capable of transitioning between V
PP
and a reference voltage level. A second transistor having a switching input thereof is coupled between the intermediate node and a reference voltage line. A substantially direct current voltage source is coupled to the input terminal of the first transistor for supplying a voltage V
HVP
less than or substantially equal to a maximum gate-to-source voltage V
GSMAX
of the first transistor. In a preferred embodiment, the voltage V
HVP
is also less than or substantially equal to a maximum drain-to-source voltage V
DSMAX
of the second transistor plus a threshold voltage V
t
of the first transistor.
Further provided herein is a transistor protection method for a switching circuit having an output transitioning between a first supply voltage V
PP
and a reference voltage level and an input transitioning between a second supply voltage level V
CC
and the reference voltage level wherein V
PP
>2*V
CC
. The method comprises the steps of providing at least two transistors in series between the output and the reference voltage level, providing a substantially direct current voltage V
HVP
to a gate terminal of a first transistor, wherein V
HVP
is less than or substantially equal to a maximum gate-to-source voltage V
GSMAX
of the first transistor and coupling the input to a gate terminal of the second transistor. In accordance with a preferred method, the substantially direct current voltage V
HVP
is less than or substantially equal to a maximum drain-to-source voltage V
DSMAX
of the second transistor plus a threshold voltage V
t
of the first transistor.


REFERENCES:
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patent: 5729155 (1998-03-01), Kobatake
patent: 5748025 (1998-05-01), Ng et al.
patent: 5777497 (1998-07-01), Han
patent: 5917348 (1999-06-01), Chow
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patent: 6580306 (2003-06-01), Hardee
Hodges et al, Analysis And Design Of Digital Integrated Circuits, 1988, McGraw-Hill, Inc., 2ndEdition, pp. 91-92.

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