High voltage tolerant switch constructed for a low voltage CMOS

Details High voltage tolerant switch constructed for a low voltage CMOS High voltage tolerant switch constructed for a low voltage CMOS

1993-03-31

1995-03-21

Sikes, William L.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

257334, 257350, 257365, 257371, 327581, 327530, 327543, H01L 2978, G06F 126

Patent

active

053999177

ABSTRACT:
An integrated circuit which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. These devices have been found capable of transferring ten or more volts to circuitry for programming or erasing flash EEPROM cells even the they are a part of integrated circuitry designed for only 3.3 volt usage.

REFERENCES:
patent: 4119996 (1978-10-01), Jhabvala
patent: 5274828 (1993-12-01), McAdams

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