High-voltage tolerant input buffer circuit

Details High-voltage tolerant input buffer circuit High-voltage tolerant input buffer circuit

2007-01-16

2007-01-16

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S108000, C327S112000, C326S081000

Reexamination Certificate

active

11146912

ABSTRACT:
The present invention provides a high-voltage tolerant input buffer circuit including a first NMOS transistor having its source terminal connected to the input pin, its gate terminal connected to a first reference voltage and its drain terminal connected to a first output terminal; a second NMOS transistor having its gate terminal connected to said first reference voltage and its source terminal connected to said first output terminal; a first PMOS transistor having its gate terminal connected to the drain terminal of said second NMOS transistor, its drain terminal connected to a second reference voltage lower than said first reference voltage and its source terminal connected to a second output terminal; a second PMOS transistor having its drain terminal connected to the drain terminal of said second NMOS transistor, its source terminal connected to said second output terminal, and its gate terminal connected to a control voltage; and a third PMOS transistor having its drain terminal connected to said second output terminal, its source terminal connected to a supply voltage, and its gate terminal connected to said control voltage.

REFERENCES:
patent: 5933027 (1999-08-01), Morris et al.
patent: 5952848 (1999-09-01), Morris
patent: 6236236 (2001-05-01), Chen
patent: 6346829 (2002-02-01), Coddington
patent: 6784717 (2004-08-01), Hunt et al.
patent: 2005/0024101 (2005-02-01), Reed et al.

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