Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2006-05-09
2006-05-09
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
Reexamination Certificate
active
07042689
ABSTRACT:
The invention describes structures and a process for providing ESD semiconductor protection with reduced input capacitance that has special advantages for high frequency analog pin I/O applications. The structures consist of a first and second NMOS serial pair whose capacitance is shielded from the I/O pins by a serial diode. The first serial pair provides an ESD voltage clamp between the I/O pin and the Vcc voltage source. The second pair provides an ESD voltage clamp between the I/O pin and Vss, or ground voltage source. A NMOS device whose gate is dynamically coupled to the ESD energy through capacitance and a RC network enhances the triggering of both pairs. The serial pairs can be used separately to match specific application requirements or used together.
REFERENCES:
patent: 5477414 (1995-12-01), Li et al.
patent: 6008970 (1999-12-01), Maloney et al.
patent: 6060752 (2000-05-01), Williams
patent: 6284616 (2001-09-01), Smith
Richier et al., Investigation of Different ESD Protection Strategies Devoted to 3.3 V RF Applications (2 Ghz) in a 0.18μm CMOS.
Process,“ EOS/ESD Symposium 2000, pp. 251-259. Leroux et al., ” A 0.8-dB NF ESD-Protected 9-mW CMOS LNA.
Operating at 1.23 GHz, Proceedings of the 2001 ISSC pp. 760-765.
Ming-Dou Ker et al., ESD Protection Design on Analog Pin with Very Low Input Capacitance for High-Frequency of.
Current Made Applications, IEEE Journal of Solid-State Circuits, vol. 35, Issue 8, Aug. 2000, pp. 1194-1199.
Ming-Dou Ker et al., “Dynamic-Floating-Gate Design for Output ESD Protection in a 0.35-μm CMOS Cell Library”, Proc. of 1998 ISCAS, vol. 2, 1998, pp. 216-219.
Jackson Stephen W.
Taiwan Semiconductor Manufacturing Co. Ltd.
LandOfFree
High voltage tolerant ESD design for analog and RF... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High voltage tolerant ESD design for analog and RF..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High voltage tolerant ESD design for analog and RF... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3634389