High voltage tolerant CMOS input/output pad circuits

Details High voltage tolerant CMOS input/output pad circuits High voltage tolerant CMOS input/output pad circuits

1995-08-28

1997-07-08

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, H02H 900

Patent

active

056468091

ABSTRACT:
A high voltage tolerant CMOS output driver circuit and high voltage tolerant CMOS input receiver circuit, through the use of shield transistors and the redefinition of the substrate of the PFET devices, is provided. The invention may be incorporated for protection in integrated circuits operating with a lower power supply voltage than externally interfaced devices operating with a higher power supply voltage.

REFERENCES:
patent: 5140174 (1992-08-01), Meier et al.
patent: 5319259 (1994-06-01), Merrill
patent: 5400202 (1995-03-01), Metz et al.
patent: 5452171 (1995-09-01), Metz et al.
patent: 5550699 (1996-08-01), Diaz
Pending U.S. Pat. Application Ser No. 08/149858, to Metz, et al., for Electrostatic Discharge Protection Circuit for Integrated Circuits, Filed Nov. 10, 1993.
Pending U.S. Pat. Applications Ser. No. 08/290627, to Diaz, et al., for Hot Plug Tolerant ESD Protection for an IC, filed Aug. 15, 1994.
Pending U.S. Pat. Application Ser. No. 08/455473, to Motley, et al., for Compensating Programmable Output Driver, filed May 31, 1995.

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