Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive
Reexamination Certificate
2000-06-02
2003-04-01
Huynh, Kim (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Transient responsive
C361S056000, C257S355000, C327S313000
Reexamination Certificate
active
06542346
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a high-voltage tolerance input buffer that can sustain an input signal having a voltage level higher than the power source of the input buffer as well as a ESD protection circuit thereto pertained.
2. Description of the Related Art
As the feature size of a semiconductor chip is decreased due to advancements in the semiconductor manufacturing technology, the voltage level of the integrated circuit (IC) carried by the chip is also decreased. Nonetheless, a system provider, such as a computer motherboard manufacturer, will need to solve the problem of integrating ICs of different voltage levels each manufactured by a different process or technology, into one useful circuit. For example, the input buffer of an IC manufactured by a more advanced technology may not correctly receive the output signal of another IC manufactured by a less advanced technology. In addition, since the voltage level of the more advanced IC is typically lower than that of the less advanced IC, the input buffer of the more advanced IC therefore can not be sufficiently protected during circuit integration. In spite of the above-mentioned integration problem, it is inevitable that the system providers will need to find a way for coping with the different voltage levels of different ICs while trying to keep the cost down. Therefore, a high-voltage tolerance input buffer capable of sustaining an input signal with a voltage level higher than the power source of the input buffer has now been devised by industrial practices as a general solution for solving the above problems.
Referring to
FIG. 1
,
FIG. 1
illustrates an input buffer of a prior art. The input buffer shown in
FIG. 1
employs two clamping diodes
10
and
12
for clamping the voltage of a pad
14
into the inner circuit
16
, which prevents the voltage received by the inner circuit
16
from being higher than the power rail VDD or lower than the power rail VSS. However, when the input buffer
10
in
FIG. 1
receives a direct current (DC) input signal higher than VDD, the power VDD will be forced to charge-up, which causes a malfunction in the inner circuit
16
. It therefore implies that the input buffer
10
in
FIG. 1
can never be a high-voltage tolerance input buffer.
Referring to FIG.
2
and
FIG. 3
,
FIG. 2
illustrates another prior art where an input buffer is provided with two semiconductor control rectifiers (SCRs).
FIG. 3
is a cross-section of one of the semiconductor control rectifiers illustrated in FIG.
2
. The input buffer shown as a prior art not only is a cause for malfunction but also a cause for gate oxide aging. If a voltage signal higher than the VDD is present at the pad
14
, all the nodes electrically connected to the pad
14
, such as the gate of NMOS
18
and the two terminals of the two semiconductor control rectifiers (SCRs)
20
, will receive the same higher voltage signal. Because the gate oxide of an IC is always designed to sustain the highest differential voltage allowable in the IC for manufacturing considerations, which is the differential voltage between the VDD and the grounded VSS. As a result, the higher voltage signal at the pad
14
will tend to be over-stressed, causing a rapid aging of the gate oxide in the NMOS
18
(or more specifically in the region
22
shown in FIG.
2
), which can turn into a reliability problem. By the same token, the NMOS
24
of the SCR
20
, as shown in
FIG. 3
, also faces the same problems of over-stressing and rapid aging. In particular, the gate of MOS
24
will receive the same higher voltage signal as present at the pad
14
. As a result, the gate oxide (or more specifically the region
26
shown in
FIG. 3
) is over-stressed since the P-substrate is typically grounded.
Referring to
FIG. 4
,
FIG. 4
illustrates a high-voltage tolerance input buffer of another prior art. As a solution for solving the gate oxide-aging problem, a depletion MOS
32
is added in series between the pad
14
and the inner circuit
30
to shielf the inner circuit
30
from the conduction of any voltage higher than the VDD. However, in order to implement the depletion MOS, one more mask and several more additional process stes will need to be inserted into the original process flow, which can dramatically increase the production cost.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a high-voltage tolerance input buffer for solving the problem integrating ICs of different voltage levels in a circuit without incurring any change in the relating semiconductor manufacturing process. By incorporating a smart circuit design of the present invention, the voltage at the gate of the NMOS can be safeguarded to levels not higher than the power VDD, thus rapid aging of the gate oxide can be prevented.
Accordingly, the present invention achieves the above-indicated object by providing a high-voltage tolerance input buffer which is coupled to the pad of an integrated circuit. Furthermore, the high-voltage tolerance input buffer comprises a voltage-sharing circuit and a switch circuit, wherein the voltage-sharing circuit is coupled between the pad and a power rail and generates a reference voltage not higher than the voltage of the pad. On the other hand, the switch circuit is coupled to the voltage-sharing circuit, which comprises a control gate to control the switching of the switch circuit according to the reference voltage.
The present invention further provides a high-voltage tolerance electrostatic discharge (ESD) protection circuit, which is coupled to the pad of an integrated circuit. The high-voltage ESD protection circuit comprises a voltage-sharing circuit and a semiconductor control rectifier (SCR), wherein the voltage-sharing circuit is coupled between the pad and a power rail and generates a reference voltage not higher than the voltage of the pad. The SCR is coupled to the voltage-sharing circuit and comprises a first n-type MOS transistor. Moreover, a first n-type MOS transistor comprising a gate is used to trigger the SCR for releasing an ESD stress according to the reference voltage.
Accordingly, different circuit structures are provided for implementing the voltage-sharing circuit of the present invention, wherein the main concept involves that the voltage-sharing circuit generates a reference voltage not higher than the VDD to prevent rapid aging of the gate oxide. The voltage-sharing circuit of the present invention comprises diodes, resisters, capacitors etc. connected in series, and the reference voltage comprises the voltage at one of the connection nodes of the devices.
REFERENCES:
patent: 4833342 (1989-05-01), Kiryu et al.
patent: 5339078 (1994-08-01), Vernon
patent: 5559479 (1996-09-01), Ohmori et al.
patent: 5617283 (1997-04-01), Krakauer et al.
patent: 5703807 (1997-12-01), Smayling et al.
patent: 5781388 (1998-07-01), Quigley
patent: 6066973 (2000-05-01), Sekino et al.
patent: 6337787 (2002-01-01), Tang
Chen Wei-Fan
Lee Shu-Chuan
Lin Shi-Tron
Yu Ta-Lee
Birch & Stewart Kolasch & Birch, LLP
Huynh Kim
Winbond Electronics Corp.
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