High voltage tolerable input buffer

Details High voltage tolerable input buffer High voltage tolerable input buffer

1998-07-31

1999-10-12

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327333, H03K 5153

Patent

active

059660350

ABSTRACT:
An input buffer includes an n-channel FET having a drain region coupled to the V.sub.cc voltage supply, a source region coupled to the output terminal and a gate electrode coupled to the input terminal. A bias circuit maintains a voltage at the source of the n-channel FET which is greater than the V.sub.SS supply voltage when a logic low voltage is applied to the input terminal.

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