1986-03-14
1988-06-21
Larkins, William D.
357 2, 357 59, 357 238, H01L 2978, H01L 2704
Patent
active
047528141
ABSTRACT:
A high voltage amorphous silicon thin film transistor including a gate electrode which controls the injection of charge carriers from a superimposed n+ doped amorphous silicon source electrode into an amorphous silicon charge carrier transport layer, spaced from the gate electrode by a dielectric layer, for causing current conduction through the transport layer to a laterally offset drain electrode. The source electrode is in charge injecting contact with the transport layer and the drain electrode is in collecting contact with the transport layer.
REFERENCES:
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patent: 4601096 (1986-07-01), Calviello
Sze, Physics of Semiconductor Devices (1st Ed., Wiley, NY, 1969), pp. 568-569.
Electronics & Communications in Japan, vol. 644, No. 12, Dec. 1981, pp. 96-104, Scripta Publishing Co., Silver Spring, Maryland, I. Yoshida et al.: "A Composite Gate Structure for Enhanced-Performance Power MOS FET's": p. 97, para 2, p. 98, FIG. 2.
Proceedings of the 14th Conference (1982 International) on Solid State Devices, Tokyo, 1982, Japanese Journal of Applied Physics, vol. 22, 1983, Supplements No. 22-1, pp. 487-491, Tokyo, JP, M. Matsumura, "Amorphous Silicon Transistors and Integrated Circuits": FIG. 1.
Abend Serge
Larkins William D.
Xerox Corporation
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