Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1998-06-25
2001-01-09
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C365S226000
Reexamination Certificate
active
06172553
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to high voltage steering networks generally and, more particularly, to a high voltage steering network for use in a EEPROM/FLASH memory.
BACKGROUND OF THE INVENTION
Non-volatile memories such as EEPROM and FLASH memories generally require a variety of voltages that may be above the positive supply voltage or below the negative supply voltage. To generate the programming voltages, pump circuits may be used in a circuit where both high positive voltages and high negative voltages are required, conventional approaches often implement separate charge pumps to generate each of the separate voltages. Once generated, said separate voltages are transferred independently from each other to the different blocks of the circuit. This implies that the receiving blocks must handle both a high positive voltage signal and a high negative voltage on separate inputs. In order to do so, each receiving block may need additional local circuitry implemented on the die. Where a number of different blocks require the high positive voltage and the high negative voltage, as is the case in EEPROM/FLASH memories, additional circuitry, such as local charge pumps, may have to be duplicated on each wordline as was implemented in U.S. Pat. No. 5,311,480. The more places the high positive voltage and the low negative voltage are required, the more circuit area may be required. Were it feasible to combine said separate high positive voltage and separate high negative voltage into a single input, then the receiving blocks would only need to handle high voltage from a simple input instead of from two inputs which would significantly reduce the die area. This invention proposes a method and a circuit to combine said separate high positive voltage and separate high negative voltage onto a single output.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a high voltage positive switch and a steering network. The high voltage positive switch may be configured to present first and second switch signals in response to a first select signal. The steering network may be configured to present a high voltage output that may transition between a very high positive and a very low negative voltage, where the transition may respond to a high voltage positive input, a low voltage negative input, a first and second switch signal, and a second select signal.
The objects, features and advantages of the present invention include providing a circuit capable of alternately steering a very high positive voltage (e.g., VPP) or a very low negative voltage (e.g., VNN) to a single output using a very small, area-efficient steering network.
REFERENCES:
patent: 4897774 (1990-01-01), Bingham et al.
patent: 4935644 (1990-06-01), Tsujimoto
patent: 5059815 (1991-10-01), Bill et al.
patent: 5276646 (1994-01-01), Kim et al.
patent: 5311480 (1994-05-01), Schreck
patent: 5319604 (1994-06-01), Imondi et al.
patent: 5371705 (1994-12-01), Nakayama et al.
patent: 5438542 (1995-08-01), Atsumi et al.
patent: 5461557 (1995-10-01), Tamagawa
patent: 5592430 (1997-01-01), Ohtsuki
patent: 5701272 (1997-12-01), Brennan, Jr.
patent: 5757228 (1998-05-01), Furutani et al.
patent: 5767735 (1998-06-01), Javanifard et al.
patent: 5796656 (1998-08-01), Kowshik et al.
patent: 5812459 (1998-09-01), Atsumi et al.
patent: 5841696 (1998-11-01), Chen et al.
patent: 5889664 (1999-03-01), Oh
IEEE JSSC, vol. 27, No. 11, Nov. 1992, A 5V-only Operation 0.6-&mgr;m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure, A. Umezawa, et al.
“Non-Volatile Semiconductor Memories, Technologies, Design and Applications”, IEEE Press, Ed Chenming Hu, 1991, JSCCC Dig. Tech.
IEEE JSSC, vol. 24, No. 5, Oct. 1989, “Analysis and Modeling of On-Chip High-Voltage Generator Circuits for Use in EEPROM Circuit”, Witters, et al.
IEEE JSSC, vol. 32, No. 6, Jun. 1997, “Efficiency Improvement in Charge Pump Circuits”, Wang et al.
IEEE JSSC, vol. 33,No. 1, Jan., 1998, “Internal Voltage Generator for Low Voltage Quarter-Micrometer Flash Memories”, T. Kawahara, et al.
IEEE JSSC, vol. 32, No. 8, Aug. 1997, “Circuit Techniques for 1.5V Power Supply Flash Memory”, N. Otsuka and M. Horowitz.
IEEE JSSC, vol. 31, No. 11, Nov. 1996, “Bit-Line Clamped Sensing Multiplex and Accurate High Voltage Generator for Quarter-Micron Flash Memories”, T. Kawahara, et al.
IEEE JSSC, vol. 27, No. 11, Nov. 1992, A 5V-only 16Mb Flash Memory with Sector Erase Mode, T. Jinbo et al.
IEEE JSSC, vol. 32, No. 1, Jan. 1997, “Program Load Adaptive Voltage Generator for Flash Memories”, Fiocchi, et al.
IEEE JSSC, vol. SC-18, No. 5, Oct. 1983, “Control Logic and Cell Design for a 4K NVRAM”, Lee, et al.
IEEE JSSC, vol. SC-18, No. 5, Oct. 1983, “High-Voltage Regulation and Process Considerations for High-Density 5V-only E2PROM's”, Oto, et al.
IEEE JSSC, vol. SC-11, No. 4, Jun. 1976, “On-Chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique”, John F. Dickson.
Montanari Donato
Murray Kenelm
Cypress Semiconductor Corp.
Kim Jung Ho
Maiorana P.C. Christopher P.
LandOfFree
High voltage steering network for EEPROM/FLASH memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High voltage steering network for EEPROM/FLASH memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High voltage steering network for EEPROM/FLASH memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2477868