Electric power conversion systems – Current conversion – Including d.c.-a.c.-d.c. converter
Reexamination Certificate
2001-02-01
2002-01-22
Berhane, Adolf Deneke (Department: 2838)
Electric power conversion systems
Current conversion
Including d.c.-a.c.-d.c. converter
C363S021150, C363S097000
Reexamination Certificate
active
06341075
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a high voltage stabilizing circuit which generates stabilized high voltage from commercial alternating-current power to provide anode voltage to be applied to an anode electrode of a cathode-ray tube, for example.
Television receivers, projectors, and display units for personal computers which employ cathode-ray tubes (hereinafter referred to as CRTs) as display devices have widely spread.
As is well known in the art, in various display units having such CRTs, a required level of high voltage (anode voltage) needs to be supplied in a stable manner to anode electrodes of the CRTs.
Specifically, although the level of anode voltage is generally set at about 25 KV to 35 KV, the anode voltage is varied according to variations in alternating-current input voltage and a load, for example. Variations in the anode voltage may in turn vary screen sizes in a vertical and a horizontal direction of an image displayed on the CRT. In addition, variations in the anode voltage cause a bright white peak image to be distorted when displayed on the screen. As shown in
FIG. 9
for example, when an original rectangular white peak image as indicated by a solid line is displayed, the white peak image is distorted into a trapezoidal shape as indicated by a broken line.
Therefore, in practice, a so-called high voltage stabilizing circuit is provided as an anode voltage supplying circuit to stabilize anode voltage for output.
FIG. 6
is a circuit diagram showing an example of a high voltage stabilizing circuit. The high voltage stabilizing circuit shown in the figure is to be provided for a so-called multiscanning-capable display unit for a personal computer.
First,
FIG. 6
shows a rectifying and smoothing circuit comprising a bridge rectifier circuit Di and a smoothing capacitor Ci. The rectifying and smoothing circuit rectifies and smoothes commercial alternating-current power AC to provide a rectified and smoothed voltage Ei whose level is equal to that of the commercial alternating-current power AC. The rectified and smoothed voltage Ei is supplied as direct-current input voltage to a switching power supply circuit
10
.
The switching power supply circuit
10
is a DC-to-DC converter configured to provide a direct-current output voltage Eo by switching and stabilizing the inputted rectified and smoothed voltage Ei. In this case, the switching power supply circuit
10
outputs a direct-current output voltage Eo stabilized at 240 V.
The direct-current output voltage Eo is inputted to a step-down converter
20
.
The step-down converter
20
is for example formed by connecting a drain and a source of a MOS-FET switching device Q
11
in series with a choke coil CH
1
between a line of the direct-current output voltage Eo and a positive electrode of a smoothing capacitor COA and inserting a diode DD
1
between a point where the source of the switching device Q
11
and the choke coil CH
1
are connected and a primary-side ground.
The switching device Q
11
is externally driven by a driving voltage from a driving circuit
14
, which will be described later, to perform switching on the direct-current output voltage Eo. A current that flows according to switching operation by the switching device Q
11
is stored in the smoothing capacitor COA via the choke coil CH
1
and the diode DD
1
. Then, the step-down converter
20
outputs a stepped-down direct-current voltage EOA, which is a voltage across the smoothing capacitor COA.
The stepped-down direct-current voltage EOA is supplied to a voltage resonance type converter
30
.
The voltage resonance type converter
30
shown in
FIG. 6
is provided with a MOS-FET switching device Q
12
to perform externally excited single-ended operation.
In the voltage resonance type converter
30
, a drain of the switching device Q
12
is connected to a positive terminal of the stepped-down direct-current voltage EOA via a choke coil CH
2
, while a source of the switching device Q
12
is connected to the primary-side ground. A gate of the switching device Q
12
is supplied with a driving voltage outputted from a driving circuit
16
, which will be described later. The switching device Q
12
is driven for switching operation by this driving voltage.
The drain of the switching device Q
12
is also connected to a starting point of a primary winding N
1
of a flyback transformer FBT, which will be described later. In this case, an ending point of the primary winding N
1
is grounded to the primary-side ground via a direct current blocking capacitor C
11
.
Thus, switching output of the switching device Q
12
is transmitted to the primary winding N
1
of the flyback transformer FBT, whereby an alternating voltage in accordance with the switching frequency is obtained at the primary winding N
1
.
A parallel resonant capacitor Cr is connected in parallel with the drain and source of the switching device Q
12
. Capacitance of the parallel resonant capacitor Cr, inductance L
12
of the choke coil CH
2
, and leakage inductance L
1
of the primary winding N
1
side of the flyback transformer FBT form a primary-side parallel resonant circuit of the voltage resonance type converter. Although detailed description is omitted here, voltage V
2
across the resonant capacitor Cr actually forms a sinusoidal pulse waveform during an off period of the switching device Q
12
as a result of the action of the parallel resonant circuit, so that voltage resonance type operation is obtained.
Also, a clamp diode DD
2
is connected in parallel with the drain and source of the switching device Q
12
. The clamp diode DD
2
forms a path of clamp current that flows during the off period of the switching device Q
12
.
The switching devices Q
11
and Q
12
on the primary side are driven for switching operation by the following configuration.
On the basis of a horizontal synchronizing signal frequency fH corresponding to a currently set resolution, a synchronizing circuit
11
generates and outputs a horizontal synchronizing signal having the frequency fH. Since the high voltage stabilizing circuit in this case is to be provided for a multiscanning display unit, the horizontal synchronizing signal frequency fH is varied within a range of 30 KHz to 120 KHz, for example.
In this case, the horizontal synchronizing signal generated by the synchronizing circuit
11
is inputted to an oscillating circuit
12
. The oscillating circuit
12
converts the horizontal synchronizing signal into an oscillating frequency signal to be used for driving the switching devices Q
11
and Q
12
, and outputs the converted signal to a PWM control circuit
13
and a driving circuit
16
.
The driving circuit
16
generates a driving voltage for driving the switching device Q
12
from the inputted oscillating frequency signal, and outputs the driving voltage to the gate of the switching device Q
12
. Thus, the switching frequency of the switching device Q
12
coincides with the currently set horizontal synchronizing signal frequency fH.
The PWM control circuit
13
effects PWM control of the inputted oscillating frequency signal on the basis of a detection output from an error amplifier circuit
15
. Specifically, the PWM control circuit
13
variably controls a duty ratio of an on/off period in one cycle of the oscillating frequency signal, and outputs the result to a driving circuit
14
. The driving circuit
14
generates driving voltage using a PWMed oscillating frequency signal outputted from the PWM control circuit
13
, and outputs the signal to the switching device Q
11
. Thus, the switching frequency of the switching device Q
11
also coincides with the currently set horizontal synchronizing signal frequency fH. This means that both the switching device Q
11
and the switching device Q
12
are allowed to perform switching operation at a switching frequency in synchronism with the horizontal synchronizing signal frequency fH. It should be noted that a duty ratio of an on/off period in one switching cycle of the switching device Q
12
is governed by the waveform (duty ra
Berhane Adolf Deneke
Frommer William S.
Frommer & Lawrence & Haug LLP
Sony Corporation
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