High voltage semiconductor devices comprising integral JFET

Details High voltage semiconductor devices comprising integral JFET High voltage semiconductor devices comprising integral JFET

1982-07-01

1985-01-15

Clawson, Jr., Joseph E.

357 22, 357 38, 357 89, H01L 2702

Patent

active

044941340

ABSTRACT:
A P-N diode includes a P.sup.- substrate with a thin N.sup.- epitaxial layer thereon. A P.sup.+ isolation region surrounds the periphery of the N.sup.- epitaxial layer and is integrally connected to the P.sup.- substrate. An N.sup.+ cathode region extends into the N.sup.- epitaxial layer from the upper surface of such layer. A P.sup.+ anode region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region. A further P.sup.+ region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region, and, in turn, is surrounded by the P.sup.+ anode region. The further P.sup.+ region is biased at the same potential as the P.sup.- substrate. An N.sup.+ buried layer is situated between the P.sup.- substrate and the N.sup.- epitaxial layer, beneath the P.sup.+ anode region, and surrounds the N.sup. + cathode region. An N.sup.+ sinker region extends into the N.sup.- epitaxial layer from its upper surface and terminates in integral contact with the N.sup.+ buried layer, the N.sup.+ sinker region surrounding the P.sup.+ anode region, and, in turn, being surrounded by the P.sup.+ isolation region. The N.sup.+ buried layer reduces parasitic currents in the P-N diode, and the further P.sup.+ region, appropriately biased, enables the P-N diode to block current at high reverse voltages. An N-P-N transistor is structurally similar to the P-N diode, having an additional N.sup.+ emitter region diffused into a P.sup.+ base region, corresponding to the P.sup.+ anode region of the P-N diode.

REFERENCES:
patent: 3812405 (1974-05-01), Clark
patent: 3878551 (1975-04-01), Callahan
J. Porter, "JFET-Transistor Yields Dev. W. Neg. Resistance," IEEE Trans. on Elec. Dev., Sep. 1976, vol. ED-23 #9, pp. 1098, 1099.
J. A. Appels & H. M. J. Vaes, "High Voltage Thin Layer Devices (RESURF Devices)", Proceedings of the 1979 IEEE International Electron Device Meeting, pp. 238-241.
S. Colak, B. Singer & E. Stupp, "Design of High-Density Power Lateral DMOS Transistors", Proceedings of the 1980 IEEE Power Electronics Specialists Conference, pp. 164-167.
R. S. Muller & T. I. Kamins, Device Electronics for Integrated Circuits, New York: John Wiley & Sons (1977), pp. 228-235.
A. B. Glaser & G. E. Subak-Sharpe, Integrated Circuit Engrg.-Design, Fabricating & Applications, Reading, Mass.: Addison-Wesley Co., (1979), pp. 254-255.

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