Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...
Reexamination Certificate
1999-05-12
2001-02-27
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including high voltage or high power devices isolated from...
C257S510000, C257S499000, C257S349000, C257S513000, C257S520000
Reexamination Certificate
active
06194772
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integration of high-voltage devices and low-voltage devices, and more particularly, to high-voltage semiconductor devices having a trench structure.
2. Description of the Prior Art
As the scale of integrated circuits (ICs) has been rapidly decreased, the design and layout rule has become more stringent. Moreover, as the integrated circuits (ICs) are fabricated to be more compact, the integration of ICs with different application has become more indispensable.
FIG. 1
shows the cross section of a conventional high-voltage complimentary metal-oxide-semiconductor (HV-CMOS) transistor, which usually includes a p-type substrate
10
, field oxide regions
4
, an n+ source region
2
, an n+ drain region
2
A, a gate region
3
, and an oxide layer
5
. In the structure of the shown transistor, the structure of its drift region generally adopts conventional local oxidation (LOCOS) technique, which has a horizontal or lateral configuration. On the other hand, low-voltage semiconductor devices in the deep-submicron semiconductor technology (e.g., less than 0.25 micrometer) largely utilize a trench oxide structure, which has a vertical configuration, to save chip area. Accordingly, in the present semiconductor industry, the difference of the used configuration becomes a bottleneck for the integration of the high-voltage devices and the low-voltage devices. Moreover, the conventional high-voltage devices suffer current driving capability when the structure is scaled down.
For the foregoing reasons, there is a need for disclosing a structure and a method of fabricating high-voltage semiconductor devices having an improved current driving capability, and facilitating the integration with the low-voltage semiconductor devices.
SUMMARY OF THE INVENTION
In accordance with the present invention, a structure is provided for high-voltage semiconductor devices that have trench structure, substantially facilitating the integration of the high-voltage devices and the low-voltage devices. Moreover, the present invention provides a structure for improving the current driving capability of the high-voltage devices. In one embodiment, the present invention includes a semiconductor substrate having a first conductivity type, and at least two oxide regions respectively refilled in at least two trenches in the substrate, one of the oxide regions being spaced from the other of the oxide regions by a channel region. The present invention also includes a silicon oxide layer encompassing each of the oxide regions on its sidewall surface and its bottom surface. At least two drift regions having a second conductivity type opposite to the first conductivity type are formed, each of the drift regions being adjacent to and in contact with the corresponding silicon oxide layer of each of the oxide regions respectively. Further, a polysilicon gate region is formed on the substrate, wherein the polysilicon gate region covers the channel region and portions of the oxide regions. A source region having the second conductivity type adjacent to one of the oxide regions is formed, wherein the source region is spaced from the channel region by such adjacent oxide region. Further, a drain region having the second conductivity type adjacent to the other one of the oxide regions is formed, wherein the drain region is spaced from the channel region by such adjacent oxide region. Finally, the invention includes at least two implanted well regions having the second conductivity type, each of the implanted well regions being adjacent to one of the oxide regions, and each of the implanted regions being spaced from the channel region by such adjacent oxide region.
REFERENCES:
patent: 4506435 (1985-03-01), Pliskin et al.
patent: 4926233 (1990-05-01), Hutter
patent: 5291049 (1994-03-01), Morita
patent: 5350941 (1994-09-01), Madan
patent: 5859466 (1999-01-01), Wada
patent: 1-189173 (1989-07-01), None
patent: 3-290961 (1991-12-01), None
Fenty Jesse A
Saadat Mahshid
United Microelectronics Corp.
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