High voltage semiconductor device and method

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357 49, 357 48, 357 55, 357 56, 357 20, 357 47, H01L 2704, H01L 2712, H01L 2906, H01L 2702

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049740504

ABSTRACT:
An improved method and structure for high voltage semiconductor devices capable of blocking voltages of the order of 1000 volts and greater is described. In a preferred embodiment, a blanket P layer is formed in an N.sup.- epi-layer on an N.sup.+ substrate. An annular groove is etched through the blanket P layer into the N.sup.- epi-layer. The bottom of the groove is doped N.sup.+ using the same mask as for the first groove etch. A second groove is formed inside of and partly overlapping the first groove and extending to a greater depth than the first groove, but not through the epi-layer. The second groove is fileld with passivating material, metal electrodes are applied to the P.sup.+ region and the N.sup.+ substrate, and the devices separated at the N.sup.+ region lying outside the second groove in the bottom of the first groove. Excellent high voltage blocking characteristics are obtained with the same or fewer process steps and better yield.

REFERENCES:
patent: 3772577 (1973-11-01), Planey
patent: 4148053 (1979-04-01), Bosselaar et al.
patent: 4298881 (1981-11-01), Sakurada et al.
patent: 4484214 (1984-11-01), Misawa et al.
patent: 4546538 (1985-10-01), Suzuki
patent: 4904617 (1990-02-01), Muschke

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