Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-06-28
2004-08-31
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185230, C365S189110
Reexamination Certificate
active
06785161
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular the present invention relates high voltage regulators and voltage reduction circuits utilized in low voltage integrated circuits.
BACKGROUND OF THE INVENTION
Most integrated circuits and memory devices are designed to operate using a specific voltage power supply, such as 5V±10%, that their internal process technologies are designed to tolerate. In modem integrated circuits and memories, the need for higher voltage power supplies is reduced as the process feature sizes, such as transistors, are reduced and operating speeds increase. However, in many situations the externally supplied high voltage is fixed by past usage, convention, or industry specification and is unable to be easily reduced to for the lower voltage tolerant process technologies.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks”. Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation. For ease of access and management the erase blocks of a non-volatile memory device are typically arranged in “banks” or segments.
Both RAM and ROM random access memory devices have memory cells that are typically arranged in an array of rows and columns. During operation, a row (page) is accessed and then memory cells can be randomly accessed on the page by providing column addresses.
FIG. 1
shows a simplified diagram of a system
128
incorporating a Flash memory
100
of the prior art coupled to a processing device or controller
102
. The Flash memory
100
has an address interface
104
, a control interface
106
, and a data interface
108
that are each coupled to the processing device
102
to allow memory read and write accesses. Internally to the Flash memory device a control state machine
110
directs internal operation of the Flash memory device; managing the Flash memory array
112
and updating RAM control registers and non-volatile erase block management registers
114
. The RAM control registers and tables
114
are utilized by the control state machine
110
during operation of the Flash memory
100
. The Flash memory array
112
contains a sequence of memory banks or segments
116
. Each bank
116
is organized logically into a series of erase blocks (not shown). Memory access addresses are received on the address interface
104
of the Flash memory
100
and divided into a row and column address portions. On a read access the row address is latched and decoded by row decode circuit
120
, which selects and activates a row page (not shown) of memory cells across a selected memory bank. The bit values encoded in the output of the selected row of memory cells are coupled from a local bitline (not shown) to a global bitline (not shown) and detected by sense amplifiers
122
associated with the memory bank. The column address of the access is latched and decoded by the column decode circuit
124
. The output of the column decode circuit selects the desired column data from the sense amplifier outputs and coupled to the data buffer
126
for transfer from the memory device through the data interface
108
. On a write access the row decode circuit
120
selects the row page and column decode circuit selects write sense amplifiers
122
. In programming a Flash memory, a charge pump circuit
130
is first activated to provide a higher programming voltage to the floating gate memory cells of the memory array
112
than the voltage supplied to operate the memory
100
. Data values to be written are coupled from the data buffer
126
to the write sense amplifiers
122
selected by the column decode circuit
124
and written to the selected floating gate memory cells (not shown) of the memory array
112
. The written cells are then reselected by the row and column decode circuits
120
,
124
and sense amplifiers
122
so that they can be read to verify that the correct values have been programmed into the selected memory cells.
Many Flash memories support fast or “factory” programming wherein the Flash memory is rapidly programmed with data. Instead of the internal charge pump, the factory programming mode typically utilizes an exterior high voltage power source that is more capable of supplying the power and current demanded in rapid programming. This external high voltage input is typically reduced and regulated for internal use by a regulator circuit the Flash memory. In addition to Flash memories, many other integrated circuits and memories utilize such an external high voltage input and regulator for internal operations. A problem with external high voltage input in integrated circuits is that the modern process technologies are in many cases unable to tolerate the field or voltage level of the external high voltage input. Additionally, as stated above, in many situations the externally supplied high voltage is fixed by past usage, convention, or industry specification and cannot be easily altered by the integrated circuit designer.
One such manner of operating a voltage regulator off an input voltage that is higher than the process breakdown voltage level is by the utilization of a voltage reduction circuit which utilizes what is termed “back bias”. In voltage reduction circuits utilizing back bias, an input MOS transistor(s) that is coupled to the external input voltage is formed in one or more separate isolation wells, isolated from the rest of the integrated circuit. Isolation wells are electrically isolated wells created by forming a well of oppositely doped silicon in the bulk material that, in turn, contains an area of silicon that is doped the same as the bulk, (i.e., a N-doped well in a P-doped bulk, containing a P-doped well material) creating an inherent reversed biased PN diode junction that isolates the circuits formed in the well. The input transistors are “diode connected” with the gate coupled to the drain so that they operate as a two terminal device in the threshold region and drop a threshold value of voltage potential. The bulk material inside the isolation we
Leffert Jay & Polgalze, P.A.
Micro)n Technology, Inc.
Nguyen Tan T.
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