High voltage regulation circuit

Details High voltage regulation circuit High voltage regulation circuit

2001-12-28

2003-05-06

Berhane, Adolf Denske (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S315000

Reexamination Certificate

active

06559628

ABSTRACT:

This nonprovisional application claims priority under 35 U.S.C. §119(a) on patent application Ser. No. 87296/2000 filed in Korea on Dec. 30, 2000, which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a high voltage regulation circuit influencing on a noise in a device using a high voltage.
2. Description of the Background Art
FIG. 1
illustrates a high voltage regulation circuit according to a related art, which is a Tedrow, et al. regulation circuit disclosed in U.S. Pat. No. 5,497,119.
Referring to
FIG. 1
, a high voltage regulation circuit according to a related art includes a sample/hold circuit
501
and a regulator circuit
503
. In this case, an input voltage V
IN
is a program voltage Vpp, and an output voltage V
OUT
is a gate voltage applied to gates of memory cells for programming.
The sample/hold circuit
501
is constructed with an input circuit
505
producing a reference voltage Vref by sampling an input voltage V
IN
, a switch
510
switching the produced reference voltage Vref in accordance with a sample enabling signal SMPLEN, and a voltage reference circuit
515
holding the reference voltage Vref inputted through the switch
510
for a predetermined time. In this case, the input circuit
505
is constructed with a pair of identical resistors R
1
and R
2
functioning as a voltage distributor and the switch
510
is constructed with an NMOS transistor N
1
. The voltage reference circuit
515
is constructed with a capacitor C
1
.
The regulator circuit
503
is constructed with an OP(operational) amplifier
520
of which the non-inversion terminal is connected to an output terminal of the voltage reference circuit
515
and of which the inversion terminal is connected to its output terminal and a programmable divider circuit
525
adjusting the range of the output voltage V
OUT
by dividing an output voltage of the OP amplifier
520
.
The programmable divider circuit
525
is constructed with a plurality of identical resistors R
3
to Rk connected in series between an output terminal of the OP amplifier
520
and a ground Vss and a plurality of NMOS transistors N
2
to Nk connected in parallel between an output terminal of the circuit
525
and one of the nodes of each of the resistors R
3
to Rk so as to switch the output voltage V
OUT
. In this case, operations of a plurality of the NMOS transistors N
2
to Nk are controlled by a control voltage provided by a control engine(not shown in the drawing) in accordance with an algorithm.
Operation of the high voltage regulation circuit is explained as follows by referring to FIG.
1
. The input circuit
505
produces a reference voltage Vref having a Vpp/2 level by sampling an input voltage V
IN
of a Vpp level using the resistors R
1
and R
2
. Under the condition of this state, the NMOS transistor N
1
of the switch
510
becomes turned on if a sample enabling signal SMPLEN becomes a high level. Then, the capacitor C
1
of the voltage reference circuit
515
is charged with the reference voltage Vref produced by the input circuit
505
through the turned-on NMOS transistor N
1
.
Subsequently, when the sample enabling signal SMPLEN becomes a low level the input circuit
505
is disconnected from the voltage reference circuit
515
. Thus, the capacitor C
1
, of the voltage reference circuit
515
holds the charged reference voltage Vref for a predetermined time(about 1 msec).
Therefore, the regulator circuit
503
determines a resistance ratio in the programmable divider circuit
525
to determine a level of an output voltage V
OUT
, and then regulates the output voltage V
OUT
in accordance with the determined resistance ratio by taking the reference voltage Vref, which is a non-inversion input of the OP amplifier, as a reference. In this case, the output voltage V
OUT
is determined by the following formula.
Output Voltage V
OUT
=Vref * (1+R
3
/Rt), wherein Rt is a total resistance determined by the programmable divider circuit
525
.
Namely, each of the resistors R
3
to Rk has the same value as the others so as to provide output voltages V
OUT
increasing constantly. Thus, the control engine defines a maximum voltage, a minimum voltage and a step size effectively so as to provide an output voltage V
OUT
asked by a specific programming algorithm for the embodiment. For example, a range of the output voltage V
OUT
is established between 2.7V and 10.8V wherein a level of the output voltage may increase by 20 mV. In this case, a voltage at an output terminal of the OP amplifier
520
is 10.8V and a voltage of the resistor Rk becomes 2.7V.
After the regulation of the output voltage V
OUT
has been completed, the control engine turns on one of the NMOS transistors N
2
to Nk so as to transfer the output voltage V
OUT
to a flash memory through the turned-on NMOS transistor.
However, if the reference voltage is changed by a noise in the high voltage regulation circuit, the output voltage varies as much as (1+R
3
/Rt) times of a reference voltage noise. Namely, the high voltage regulation circuit according to the background art fails to provide a stable output voltage due to the reference voltage noise that appears in the output voltage and is amplified by multiplication by a positive number.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a high voltage regulation circuit that substantially obviates one or more problems due to limitations and disadvantages of the background art.
An object of the present invention is to provide a high voltage regulation circuit enabling the minimization of noise influence in a device using a high voltage.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attains by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these Sects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a high voltage regulation circuit includes a high voltage regulation part regulating a high voltage by having a constant current flow through both ends of resistors of a high voltage regulator when a noise is inputted thereto, a high voltage level detection part controlling a high voltage regulation operation by detecting that an output voltage is reduced to a level equal to or lower than a predetermined level, and a current mirror part providing the high voltage regulation part with a constant current by being equipped with a current source.
Preferably, the high voltage regulation part includes a high voltage regulator, which includes a first MOS transistor connected in series a between a high voltage and a ground, a first resistor, a second resistor, a second MOS transistor, and a differential amplifier connected to the first MOS transistor, a first pass transistor connected to the first MOS transistor in parallel, a second pass transistor connected to the second MOS transistor in parallel, and a third MOS transistor connected between an output terminal of the differential amplifier and the ground.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed, description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spit and scope of the invention will become apparent to those skilled in the art from this detailed description.


REFERENCES:
patent: 3840797 (1974-10-01), Aggen et al.
patent: 4792749 (1988-12-01), Kitagawa et al.
patent: 4912393 (1990-03-01),

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