Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1999-05-21
2001-09-11
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S313000, C327S314000, C326S027000, C326S080000
Reexamination Certificate
active
06288590
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of integrated circuits. More particularly, the present invention relates to the art of input buffer design to provide a safe maximum input voltage that can be seen across a gate-to-drain or gate-to-source junction of a metal-oxide-semiconductor field effect transistor (MOSFET).
BACKGROUND INFORMATION
Integrated circuits (ICs) are used in a wide variety of electronic equipment including everything from consumer products to space probes. In the vast majority of applications, primary design constraints usually include power dissipation, heat generation, cost, and size. ICs are particularly useful because they can provide millions of transistors in a vary small package. Each transistor, however, dissipates a certain amount of power and generates a certain amount of heat. The potentially millions of transistors in an IC can consume a relatively large amount of power and dissipate a relatively large amount of heat.
In order to conserve power and reduce heat problems in ICs, core IC logic is often designed to operate at relatively low voltage levels. The low internal operating voltages of core logic are often below the normal operating voltages needed by other components. So, for instance, if ICs and other components are used together in electronic equipment, internal logic in an IC may operate at 1.8 volts, but IC input ports may experience signals from external logic of up to 5 volts.
FIG. 1
illustrates one embodiment of a prior art input buffer to convert input signals from external logic
110
to an operating voltage for core logic
120
within IC
130
. Transistors
150
and
160
are complementary metal-oxide-semiconductor (CMOS) transistors. When external logic
110
asserts a high voltage, transistor
160
turns on and transistor
150
turns off to couple core logic
120
to ground. When external logic
110
asserts a low voltage, transistor
150
turns on and transistor
160
turns off to couple core logic
120
to core operating voltage source
140
. This type of circuit cannot handle high voltage on the gate directly.
If the magnitude of the voltage asserted on the gates of transistors
150
and
160
becomes too large, electric current may arc across the transistors permanently damaging the oxides within the transistors and rendering the transistors inoperative. The maximum voltage that a transistor can withstand across the oxide, either from the gate to the source or the gate to the drain, is process dependent. That is, depending on how thick the oxide is and the profile depth of gate-source junctions and gate-drain junctions for a particular transistor technology or manufacturing process, the maximum tolerable voltage varies.
Because size is often a primary design constraint, with each new generation of integrated circuit technology, transistors within ICs, and hence oxide thicknesses, tend to become smaller and the number of transistors per chip tends to increase. Increased numbers of transistors translates into lower desired operating voltages to reduce heat and power dissipation. Thinner oxides also translate into lower maximum tolerable voltage levels. In which case, with each new generation of IC technology, the difference between internal operating voltages and external operating voltages tends to increase, but the maximum tolerable voltage drop across individual transistor oxides tends to decrease.
Continuing the above example, if the process dependent maximum tolerable voltage for transistors comprising core logic
120
in
FIG. 1
was less than the voltage asserted by external logic
110
, transistors
150
and
160
would have to be designed to withstand higher voltages than internal logic
120
. That is, in order take advantage of an IC technology that uses very small transistors in core logic
120
, transistors
150
and
160
would need to be created using a different, higher voltage technology than the internal logic in order to prevent core logic
120
from being permanently damaged by large input voltages.
Unfortunately, each additional technology on an IC tends to add cost. For instance, additional technologies usually require additional, and costly, processing steps to make different oxide thicknesses or carrier electron densities. Additional technologies also tend to make ICs more difficult and costly to design because optimizing performance for one technology may interfere with the performance of other technologies. High voltage technologies, which tend to rely on thicker oxides, also tend to operate slower and dissipate larger amounts of energy and heat.
Therefore, for at least the reasons discussed above, a need exists for an improved integrated circuit input buffer which can withstand a higher input voltage than internal logic, but does not require the addition of a higher voltage transistor technology.
SUMMARY OF THE INVENTION
The present invention provides an improved high voltage protection integrated circuit (IC) input buffer. An IC includes a number of circuit elements and an input pin. Each of the circuit elements can tolerate a process dependent maximum voltage magnitude. The input pin can be provided with a voltage magnitude that is larger than the process dependent maximum voltage magnitude of individual circuit elements. The circuit elements include a subset of internal circuit elements and a subset of input buffer circuit elements. The input buffer circuit elements couple the internal circuit elements to the input pin, and are intercoupled in accordance with a predetermined topology to accept the larger voltage magnitude provided to the input pin without damaging the circuit elements.
REFERENCES:
patent: 4858055 (1989-08-01), Okitaka
patent: 5528190 (1996-06-01), Homnigford
patent: 5696397 (1997-12-01), Sakai
patent: 5760630 (1998-06-01), Okamoto
Pending application No. 09/096,283, filed Jun. 11, 1998, entitled “A Stress-Follower Circuit Configuration”.
Pending application No. 09/096,730, filed Jun. 10, 1998, entitled “A Voltage Clamp”.
Blakely , Sokoloff, Taylor & Zafman LLP
Cunningham Terry D.
Intel Corporation
Tra Quan
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