High voltage protection circuit for improved oxide reliability

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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C361S111000, C361S091100, C361S115000

Reexamination Certificate

active

06633468

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to an integrated circuit and more particularly to a protection circuit for an integrated circuit with high voltage input signals and improved oxide reliability.
BACKGROUND OF THE INVENTION
Present complementary metal oxide semiconductor (CMOS) and bipolar-CMOS (BiCMOS) circuits employ electrostatic discharge protection (ESD) circuits to protect against electrostatic discharge due to ordinary human and machine handling. This electrostatic discharge occurs when the semiconductor circuit contacts an object that is charged to a substantially different electrostatic potential of typically several thousand volts. The contact produces a short-duration, high-current transient in the semiconductor circuit. This high current transient may damage the semiconductor circuit through joule heating. Furthermore, high voltage developed across internal components of the semiconductor circuit may damage MOS transistor gate oxide.
Sensitivity of the semiconductor circuit is determined by various test methods. A typical circuit used to determine sensitivity of the semiconductor circuit to human handling includes a capacitor and resistor that emulate a human body resistor-capacitor (RC) time constant. The capacitor is preferably 100 pF, and the resistor is preferably 1500 &OHgr;, thereby providing a 150-nanosecond time constant. A semiconductor device is connected to the test circuit at a predetermined external terminal for a selected test pin combination. In operation, the capacitor is initially charged to a predetermined stress voltage and discharged through the resistor and the semiconductor device. A post stress current-voltage measurement determines whether the semiconductor device is damaged. Although this test effectively emulates electrostatic discharge from a human body, it fails to comprehend other common forms of electrostatic discharge.
A charged-device ESD test is another common test method for testing semiconductor device sensitivity. This method is typically used to determine sensitivity of the semiconductor circuit to ESD under automated manufacturing conditions. The test circuit includes a stress voltage supply connected in series with a current limiting resistor. The semiconductor device forms a capacitor above a ground plane that is typically
1
-
2
pF. A low impedance conductor forms a discharge path having an RC time constant typically two orders of magnitude less than a human body model ESD tester. In operation, the semiconductor device is initially charged with respect to the ground plane to a predetermined stress voltage. The semiconductor device is then discharged at a selected terminal through the low impedance conductor. This connection produces a high-voltage, high-current discharge in which a magnitude of the initial voltage across the semiconductor device approaches that of the initial stress voltage.
A particular problem of protection circuit design arises when high voltage signals having a magnitude greater than the supply voltage are applied to an integrated circuit during normal operation. These high voltage signals require special circuit design techniques to avoid gate oxide stress due to a relatively high electric field. These special design techniques must be included in protection circuit design as well, because the protection circuit must remain inactive in response to the high voltage signals during normal operation yet operative in response to either human body or charged-device ESD stress. Referring to
FIG. 4
, there is an ESD protection circuit of the prior art including series-connected metal oxide semiconductor (MOS) transistors
400
and
402
arranged to conduct the ESD current between bond pad
100
and V
SS
supply terminal
130
. The control gates of these MOS transistors are held at ground or V
SS
potential by resistors R
1
406
and R
2
410
during normal circuit operation. The series connection of MOS transistors produces a higher activation voltage for the protection circuit that is greater than the normal high voltage signals. The series connected MOS transistors, therefore, remain inactive in response to normal high voltage signals at bond pad
100
. Application of ESD stress at bond pad
100
, however, capacitively couples a greater voltage at the bond pad
100
to leads
404
and
408
via the parasitic MOS gate-drain capacitance that is sufficient to induce conduction of the MOS transistors. The resulting conduction of ESD current through MOS transistors
400
and
402
limits the maximum voltage on lead
102
, thereby protecting circuit
104
.
A problem with this protection design arises from the high electric field across MOS transistor
400
during normal operation. Since lead
404
remains at ground or V
SS
potential during normal operation, the high voltage signals at lead
102
produce a high electric field across the gate oxide of MOS transistor
400
between drain
102
and gate
404
terminals. MOS transistor
400
is typically designed with the same gate oxide thickness as other MOS transistors on the integrated circuit to comprehend a normal supply voltage level. Thus, the high electric field due to the high voltage signals contributes to premature degradation of MOS transistor
400
during normal circuit operation. This degradation may take the form of transistor threshold variation or transistor gain variation as is well known in the art.
Referring now to
FIG. 5
, there is a protection circuit of the prior art as disclosed in U.S. Pat. No. 5,930,094, filed Aug. 26, 1998. This protection circuit provides bias circuits G
1
504
and G
2
506
to divide the supply voltage V
DD
at lead
120
between leads
404
and
408
during normal circuit operation. In particular, the '094 patent teaches that the voltage at lead
408
should be about equal to a threshold voltage and that the voltage at lead
404
should be two P-channel threshold voltages below the V
DD
supply voltage. At feast one of MOS transistors
400
and
402
remains off, therefore, during normal circuit operation. This circuit advantageously divides the high voltage signals at bond pad
100
across the gate oxide of MOS transistors
400
and
402
, thereby eliminating premature MOS transistor degradation.
In operation, application of ESD stress at bond pad
100
causes ESD stress current to flow through diode D
1
500
. This ESD stress current charges the parasitic integrated circuit capacitance C
C
502
between voltage supplies V
DD
120
and V
SS
130
. The resulting voltage on voltage supply V
DD
120
powers bias circuits G
1
504
and G
2
506
which, in turn, apply voltage to control gates of MOS transistors
400
and
402
. The series circuit of MOS transistors
400
and
402
consequently conducts the ESD current, thereby protecting the protected circuit
104
.
Although this protection circuit reduces the problem of premature MOS gate oxide stress during normal operation, it has significant disadvantages. First, diode D
1
limits the maximum high voltage signal at bond pad
100
to one forward-biased diode drop above supply voltage V
DD
. Second, the bias circuits depend on voltage coupled to V
DD
through diode D
1
for proper operation. Third, the time required to charge capacitor C
C
limits minimum response time of the protection circuit. Finally, both of bias circuits G
1
and G
2
include static current paths (
FIG. 4
of '094 patent) between voltage supply terminals V
DD
and V
SS
that increase standby current of the integrated circuit during normal operation.
SUMMARY OF THE INVENTION
These problems are resolved by a structure with an external terminal and a reference terminal. A first transistor has a current path coupled to the external terminal and has a first control terminal. A second transistor has a current path coupled between the current path of the first transistor and the reference terminal and has a second control terminal. A bias circuit comprises a third transistor having a first conductivity type and a fourth transistor having a second conductivity type. The third and fourth tra

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