High voltage power supply clamp circuitry for electrostatic disc

Details High voltage power supply clamp circuitry for electrostatic disc High voltage power supply clamp circuitry for electrostatic disc

1998-06-08

1999-09-21

Sherry, Michael J.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, H02H 322

Patent

active

059562196

ABSTRACT:
Clamp circuitry capable of providing ESD protection to a high voltage supply connection is provided. The clamp circuitry increases the area efficiency of ESD power supply clamping circuitry to sink larger currents during an ESD event, while maintaining backward compatibility with the higher voltage requirements of older ICs. The voltage clamp circuits include two discharge transistors which are controlled by a control circuit. The control circuit couples the gates of the discharge transistors to ground during an ESD event.

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Grove, A., Physics and Technology of Semiconductor Devices, John Wiley & Sons, Pubs., New York, 3 pages, (1967).
Merrill, R., et al., "ESD Design Methodology", Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 6 pages (Sep. 28-30, 199)
Wann, C., et al., "High-Performance 0.07-um CMOS with 9.5-ps Gate Delay and 150 GHz ft", IEEE Electron Device Letters, vol. 18, No. 12, pp. 625-627, (Dec. 1997).
Worley, E.R., et al., "Sub-micron Chip ESD Protection Schemes Which Avoid Avalanching Junctions", EOS/ESD Symposium, 9 pages, (Sep. 1995).

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