Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-02-11
2004-03-30
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185330, C365S185250, C365S204000
Reexamination Certificate
active
06714458
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuits, and more specifically to the storage of nonvolatile data in integrated circuits.
BACKGROUND OF THE INVENTION
Many battery-powered portable electronic devices, such as laptop computers, Portable Digital Assistants, digital cameras, cell phones and the like, require memory devices that provide large storage capacity and low power consumption. One type of memory device that is well-suited to use in such portable devices is flash memory, which is a type of semiconductor memory that provides relatively large and nonvolatile storage of data. The nonvolatile nature of the storage means that the flash memory does not require power to maintain the data, as will be appreciated by those skilled in the art.
A typical flash memory includes a memory-cell array having a large number of memory cells arranged in rows and columns and grouped into blocks.
FIG. 1A
illustrates a simplified cross-sectional view of a conventional flash memory cell
100
. The flash memory cell
100
is formed by a field-effect transistor
101
including an N+ source region
102
and an N+ drain region
104
formed in an isolated p-well
106
in a semiconductor substrate (not shown). A P+ region
107
is formed in the p-well
106
and is coupled to a p-well drive PWDRV that receives a voltage to bias the p-well at a required level during various modes of operation of the memory-cell
100
, as will be discussed in more detail below. A channel region
108
is defined in the p-well
106
between the source region
102
and drain region
104
. In the memory-cell array containing the flash memory cell
100
, the source region
102
is coupled to an array source AS, with all memory cells
100
in a given block in the flash memory being coupled to the same array source. The drain region
104
of each memory cell
100
is coupled to a bit line BL of the memory-cell array.
The memory cell
100
further includes a floating gate
110
formed on an oxide layer
112
over the channel region
108
, with the floating gate being capable of holding a charge from electrons that are transferred either to or from the channel region
108
through the oxide layer
112
. A control gate
114
is formed over the floating gate
110
with a dielectric layer
116
being disposed between the two gates to isolate the control gate from the floating gate. The control gate
114
of each memory cell
100
is coupled to a word line WL of the memory-cell array.
In operation, during a programming mode charge is stored on the floating gate
110
and during an erase mode charge is removed from the floating gate. The presence or absence of charge on the floating gate
110
determines a threshold voltage VT of the field effect transistor
101
so that when the word line WL is activated (i.e., applies active voltage to the control gate) the transistor either turns ON or stays OFF depending on whether charge is or isn't stored on the floating gate, as will be discussed in more detail below. In this way, the memory cell
100
stores a first logic state when the floating gate
110
stores charge and a second logic state when the floating gate does not store charge.
FIG. 1B
illustrates the operation of the memory cell
100
of
FIG. 1A
during a write mode. To write data to the memory cell
100
, which means to store a charge on the floating gate
110
and, in turn, store the corresponding logic state in the memory cell, a positive programming voltage VPP is applied through the word line WL to the control gate
114
. This positive programming voltage VPP on the control gate
114
attracts electrons
120
from the p-well
106
and causes them to accumulate toward the surface of the channel region
108
. During a write, a drain voltage VD is applied through the bit line BL to the drain
104
, and the array source AS and p-well drive PWDRV are coupled to ground to thereby couple the source
102
and p-well
106
to ground, respectively. The value of VD depends upon the process technology, and is typically 3 to 5 volts. As the drain-to-source voltage increases, electrons
120
begin to flow through the channel
108
from source
102
to drain
104
, and in the process some electrons acquire a large kinetic energy. The voltage difference between control gate
114
and the drain
104
creates an electric field through the oxide layer
116
, and this electric field attracts the electrons
120
. Some of the electrons
120
having enough kinetic energy to overcome the barrier presented by the oxide
112
. These electrons
120
are attracted to and accumulate on the floating gate
110
, which charges the floating gate. The write operation continues for a required time, and the programming voltages VPP, VD and ground applied to the word line WL, drain
104
, and source
102
, respectively, are thereafter removed.
The charged floating gate
110
raises the threshold voltage VT of the field effect transistor
101
above the active voltage applied on the word line WL during subsequent read operations. As a result, when the word line WL goes active during a read, the memory cell
100
does not turn ON and sense amplifiers (not shown) coupled to the bit line BL sense and amplify the current through the memory cell
100
and drive an output signal to a first logic state. Thus, in this situation, the sense amplifiers drive the output signal to the first logic state stored by the memory cell
100
that was previously written to or programmed. Note that during a write operation, a particular memory cell
100
in the memory-cell array is programmed to the first logic state, in contrast to an erase operation in which the data stored in a block of memory cells in the array are erased or programmed to a second logic state that is the complement of the first logic state, as will now be discussed in more detail.
FIG. 1C
illustrates the operation of the memory cell
100
of
FIG. 1B
during an erase mode. During the erase mode, the memory cell
100
is erased by discharging the floating gate
110
. To erase the memory cell
100
, the voltage VPP, which is developed on a high voltage bus HVBUS in the flash memory containing the memory cell
100
, is applied through the array source AS and p-well drive PWDRV to the source
102
and p-well
106
, respectively. A negative programming voltage −VPP is applied through the word line WL to the control gate
114
, and the drain
104
is floated or electrically isolated. In response to these applied voltages, electrons
120
stored on the floating gate
110
are attracted to the source
102
through the oxide layer
116
until the floating gate is discharged. The discharged floating gate
110
results in the threshold voltage VT of the transistor
101
being returned to a value below the active voltage applied on the word line WL during subsequent read operations. As a result, when the word line WL goes active during a read, the memory cell
100
turns ON and sense amplifiers (not shown) coupled to the bit line BL sense and amplify the current through the memory cell
100
and drive the output signal to the second logic state. Thus, in this situation, the sense amplifiers drive the output signal to the second logic state stored by the memory cell
100
that was previously erased and not thereafter written to or programmed. As previously mentioned, during the erase mode, all memory cells in a given block are erased and thus store the second logic state. The array sources AS of all memory cells
100
in a given block are coupled together. As will be understood by those skilled in the art, the HVBUS bus is a bus in the flash memory on which required voltages, including the voltage VPP, are developed, and when the voltage on the bus is to be applied to a component in the flash memory the component is simply coupled to the bus.
After erasing the memory cell
100
but prior to reading data from the memory cell, the voltages on the word line WL, array source AS, and p-well drive PWDRV must be discharged to approximately zero volts. Ideally, these v
Gualandri Stephen J.
Pekny Theodore T.
Elms Richard
Hur Jung H.
Micro)n Technology, Inc.
LandOfFree
High voltage positive and negative two-phase discharge... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High voltage positive and negative two-phase discharge..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High voltage positive and negative two-phase discharge... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3206588