High voltage on chip FET driver

Details High voltage on chip FET driver High voltage on chip FET driver

1981-03-20

1984-01-31

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307568, 307581, 307200B, 357 23, G03K 1710, G03K 17687

Patent

active

044292376

ABSTRACT:
High voltage tolerant FET circuits are characterized by the use of shield structures surrounding source/drain diffusion pockets, with the shields tied to apropriate potentials, which in some cases is the associated gate potential. Some embodiments use enhancement mode devices which however have implanted channels underlying the shield structures. Operation of several embodiments is achieved near the snap-back limits by the use of a clamp to maintain potential drop below this limit. High voltage switching at heavy loads is achieved by a voltage divider providing appropriate gate potentials to the load carrying FETs.

REFERENCES:
patent: 3454844 (1969-07-01), Dill
patent: 4069430 (1978-01-01), Masuda
patent: 4172260 (1979-10-01), Okabe et al.
patent: 4199695 (1980-04-01), Cook et al.
patent: 4288802 (1981-09-01), Ronen
patent: 4307307 (1981-12-01), Parekh
patent: 4333225 (1982-06-01), Yeh
Saraswat et al., "A High Voltage MOS Switch", IEEE Journal of Solid-State Circuits, Jun. 1979, pp. 136-142.
Hagiwara et al., "A 16K Bit Electrically Erasable PROM Using n-Channel Si-Gate MNOS Technology", IEEE Journal of Solid-State Circuits, vol. SC-15, No. 3, Jun. 1980.

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