High-voltage NMOS switch

Details High-voltage NMOS switch High-voltage NMOS switch

1997-12-12

2001-02-13

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S536000, C327S589000

Reexamination Certificate

active

06188265

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to high voltage switching, and more particularly to a more flexible system for switching between a low voltage and a high voltage at an adjustable ramp rate.
2. Description of Background of Art
An erasable programmable read-only memory (“EPROM”) is a non-volatile integrated memory circuit, which stores data in memory cells constructed from enhancement-type n-channel metal-oxide semiconductor field effect (“NMOS”) memory transistors. Each EPROM memory cell is one single memory transistor, which is logically organized into a memory array of aligned rows representing word lines and aligned columns representing bit lines. To select a memory cell for either programming or erasing, a row decoder and column decoder, each with separate high voltage switches corresponding to specific word lines and bit lines, activate the word line and bit line corresponding to the selected memory cell.
When a selected memory cell is programmed, the memory transistor of the memory cell is placed into the “0” logic state by lowering the threshold voltage level of the memory transistor to approximately 0.5V to 1V. When the memory cell is erased by a technique such as exposing the memory cell to UV light, the memory transistor is placed into the “1” logic state by increasing the threshold voltage level of the memory transistor to approximately 5V or higher.
Another type of memory device is an electrically erasable programmable read only memory (“EEPROM”). For EEPROMs, each EEPROM memory cell, unlike the EPROM memory cell, consists of two NMOS transistors, a “select” transistor and the memory transistor.
Typically, during the programming operation for the memory cells, a high voltage V
pp
of about 12 to 20 volts is transferred by the row and column decoders to the selected word line to turn “on” the select transistor of the selected memory cell. By further transferring V
pp
to the selected bit line attached to the drain electrode of the select transistor and approximately 0 volts to the control gate of the memory transistor, a small tunneling current lowers the threshold voltage of the memory transistor to approximately a range of 0.8V to −2V.
During the erasure operation, the control gate of the selected memory cell is raised to a high voltage V
pp
and the bit line of the selected memory cell is lowered to 0 volts. Since the floating gate is electrically isolated from the memory transistor, once the high voltage V
pp
is removed, a charge remains on the floating gate and the threshold voltage of the memory transistor is raised to at least approximately half of the read voltage V
cc
. V
cc
is approximately 1.5 to 6 volts.
To switch between memory cells to alter the logic states of these memory cells, the row and column decoders rely upon a plurality of high voltage NMOS switches to switch between a high and a low voltage level.
FIG. 1A
illustrates a high level schematic drawing of one of these conventional high voltage NMOS switch designs
100
which is electrically interconnected between the output of an input state logic circuit
115
and an input of a storage device
117
such as a memory array. To simplify the discussion, even though a plurality of high voltage NMOS switches
100
in conjunction with the input state logic circuit
115
comprise a decoder, only one of the high voltage NMOS switches
100
will be illustrated.
The high voltage NMOS switch
100
includes a switch
105
, a high voltage pump
107
, a power source
109
, and a connection to ground
111
. The switch
105
receives either a high or a low input logic state V
state
from an input state logic circuit
115
, which the switch
105
in turn transforms into either a distinct low or high switch output voltage level V
out
for the storage device
117
. It should be noted that the switch output voltage level V
out
can also be considered the output voltage level of the overall decoder, which is not shown.
For example, if V
state
is in a high or “1” logic state, the switch
105
connects a switch output node
125
with ground
111
resulting in the switch output voltage level V
out
dropping to 0 volts. If the switch
105
receives V
state
in a low or “0” logic state, the high voltage pump
107
ramps up V
out
to a high voltage output level V
pp
(e.g. 10-20V) based solely upon a first half-cycle of a power source waveform signal V
ps
, which is illustrated in
FIG. 3. A
more detailed description of the high voltage pump
107
will be discussed in FIG.
1
B.
FIG. 1B
is an illustration of a more detailed schematic drawing of the conventional high voltage switch
100
discussed in FIG.
1
A. The high voltage switch
100
more specifically includes three transistor switches, M
1
, M
2
, M
3
, a clamping diode transistor M
4
, two high voltage pump transistor diodes, M
5
and M
6
, a high voltage pump coupling capacitor, C
p
, and a power source
109
.
The switch
105
discussed in
FIG. 1A
consists of NMOS transistor switches M
1
, M
2
, and M
3
. Transistors M
1
and M
2
have gate electrodes which are electrically coupled together with the input state logic circuit
115
at an input node
124
. The source electrodes of M
1
and M
2
are electrically coupled to ground
111
. The drain electrode of M
1
is electrically coupled to the output of the high voltage pump
107
at node
123
as well as to the control gate electrode of transistor M
3
. The drain electrode of M
2
is electrically coupled with the output node
125
which is also electrically coupled to the source gate of transistor M
3
. The drain electrode of transistor M
3
is electrically coupled to the high voltage output level V
pp
.
As discussed above, when the input state logic circuit
115
transmits V
state
in a high logic state, transistor switches, M
1
and M
2
close and the output node
125
is connected directly with ground
111
resulting in V
out
dropping to 0 volts. When the input state logic circuit
115
transmits V
state
in a low logic state, M
1
and M
2
remain open, thereby allowing the high voltage pump
107
to begin ramping up V
out
to the high voltage output level V
pp
.
The high voltage pump
107
includes a clamping diode transistor M
4
, a coupling capacitor C
p
, and pumping transistor diodes, M
5
and M
6
. C
p
is electrically coupled to the power source
109
, which generates a power source waveform signal V
ps
having a first half-cycle at V
cc
(e.g. 5 volts) and a second half-cycle at 0 volts. As illustrated in
FIG. 3
, in the first half-cycle of the power source waveform signal V
ps
, the voltage level rises from 0 to V
cc
. During the second half-cycle of the power source waveform signal V
ps
, the voltage level drops from V
cc
to 0 volts. C
p
isolates the power source waveform signal V
ps
from the high voltage pump
107
.
Pumping transistor diodes M
5
and M
6
receive the coupled power source waveform signal V
ps
and, as illustrated in
FIG. 3
, the switch output voltage level V
out
is ramped up to higher voltage levels during only the first half of the full ramp up potential of the switch
100
. More specifically, since V
ps
continually alternates in half-cycles between a high voltage level V
cc
and 0 volts, the ramp up of V
out
only occurs during the first half-cycle (e.g. when the voltage level increases from 0 volts to V
cc
) of each full-cycle of V
ps
. The second half-cycle of V
ps
remains unused.
During this first half-cycle of V
ps
, V
121
and V
123
can be mathematically described using the following equations:
V
121
=V
ps
(
C
1
/(
C
1
+C
121
))
V
123
=V
121
−V
TM5
where C
1
is the capacitance of C
p
, C
121
is the stray capacitance of node
121
, V
ps
is approximately equal to V
cc
, and V
TM5
is the threshold voltage for transistor diode M
5
. During the second half-cycle of V
ps
, no additional ramp up of V
121
or V
123
occurs.
After each full cycle of V
ps
, V
121
and V
123
continue to ramp up during only the first half-cycle of V
ps
toward a voltage level of V
pp
+

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