High voltage MOS transistors with reduced parasitic current gain

Details High voltage MOS transistors with reduced parasitic current gain High voltage MOS transistors with reduced parasitic current gain

1992-03-11

1993-06-08

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

With means to increase current gain or operating frequency

257583, 257577, 257557, 257370, H01L 2702, H01L 2972

Patent

active

052182282

ABSTRACT:
A method is disclosed which produces a high voltage MOS transistor with a deep retrograde N-well region, which includes a buried layer, said deep retrograde well region acting to increase the breakdown voltage of the MOS transistor and reduce the current gain of the inherent parasitic bipolar transistor. To achieve a high degree of control over the impurity concentration of the buried layer without affecting the impurity concentration in the N-well region, two dopants species are diffused or implanted in the N+ buried layer: one, a slow diffusing dopant, such as antimony or arsenic, and the other, a more rapidly diffusing dopant, such as phosphorus. A P- type epitaxial layer is grown over the buried layer and an N-well is formed in the epitaxial layer over the buried layer. Using this method, the high concentration of slow diffusing N type antimony or arsenic dopant in the buried layer will not out-diffuse into the N-well region and adversely affect the breakdown voltage between the source or drain and the N-well. The out-diffusing of the phosphorus into the epitaxial layer, however, will merge with the phosphorus diffusion from the top to form a uniform N type concentration in the N-well.

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Latch-Up in CMOS Technology, R. Troutman, Kluwer Academic Publishers, Boston 1986.

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