1987-04-24
1989-03-07
James, Andrew J.
357 22, 357 234, 357 238, H01L 2702, H01L 2978, H01L 2980
Patent
active
048110752
ABSTRACT:
An insulated-gate, field-effect transistor and a double-sided, junction-gate field-effect transistor are connected in series on the same chip to form a high-voltage MOS transistor. An extended drain region is formed on top of a substrate of opposite conductivity-type material. A top layer of material having a conductivity-type opposite that of the extended drain and similar to that of the substrate is provided by ion-implantation through the same mask window as the extended drain region. This top layer covers only an intermediate portion of the extended drain which has ends contacting a silicon dioxide layer thereabove. The top layer is either connected to the substrate or left floating. Current flow through the extended drain region can be controlled by the substrate and the top layer, which act as gates providing field-effects for pinching off the extended drain region therebetween. A complementary pair of such high-voltage MOS transistors having opposite conductivity-type are provided on the same chip.
REFERENCES:
patent: 4626879 (1986-12-01), Colak
patent: 4628341 (1986-12-01), Thomas
Sze, Physics of Semiconductor Devices Wiley & Sons N.Y. c. 1981 pp. 431-438, 486-491.
Jackson Jerome
James Andrew J.
Power Integrations, Inc.
Schatzel Thomas E.
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