High voltage merged bipolar/CMOS technology

Details High voltage merged bipolar/CMOS technology High voltage merged bipolar/CMOS technology

1987-11-13

1991-02-19

Carroll, J.

357 40, 357 48, 357 90, H01L 2702, H01L 2704

Patent

active

049948873

ABSTRACT:
An integrated circuit having PMOS, NMOS and NPN transistors is described for applications in which both digital and analog circuits are required. The integrated circuit is designed to allow standard CMOS cells to be used in the integrated circuit without redesign. A P+ substrate (48) is provided upon which a first P- epitaxy layer (46) is formed. N+ DUF regions (50,52) are provided for the PMOS and NPN transistors, respectively. The base region (68) is formed in an Nwell (58) by implantation and diffusion. Before diffusion, a nitride layer (70) is formed over the base (68) to provided an inert annealing thereof. The base diffusion and collector diffusion occurs before the CMOS channel stop and source/drain diffusions in order to prevent altering diffusion times for the MOS transistors.

REFERENCES:
patent: 3899793 (1975-08-01), Wakamiya et al.
patent: 4272307 (1981-06-01), Mayrand
patent: 4497106 (1985-02-01), Momma et al.
patent: 4546370 (1985-10-01), Curran
patent: 4628341 (1986-12-01), Thomas
patent: 4818720 (1989-04-01), Iwasaki
patent: 4825275 (1989-04-01), Tomassetti

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