High voltage isolation circuit for CMOS networks

Details High voltage isolation circuit for CMOS networks High voltage isolation circuit for CMOS networks

1985-05-29

1987-06-09

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307579, 307585, 307296R, 307200B, H03K 19096, H03K 17687, H03K 1920

Patent

active

046722416

ABSTRACT:
A high voltage isolation circuit for CMOS networks includes a N-channel MOS pass transistor for isolating a high voltage node from a low voltage node so as to prevent CMOS latch-up. There is provided a substrate of N-conductivity type and a P-conductivity region diffused in the substrate to form a PN junction. A supply potential is applied to the substrate. The pass transistor has a conduction path and a control electrode in which one end of the conduction path defines a first node for receiving thereat a first voltage, and the other end of the conduction path defines a second node for receiving thereat a second voltage. The first node is connected to the P-conductivity region. During a first mode of operation, the pass transistor is rendered more conductive so that the first node is coupled to the second node so that the second voltage follows the first voltage. During a second mode of operation, the pass transistor is rendered less conductive so that the second node is isolated from the first node so that the second voltage, which is allowed to be charged higher than the supply potential, is prevented from being applied to the P-conductivity region thereby avoiding latch-up.

REFERENCES:
patent: 4115710 (1978-09-01), Lou

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