High-voltage input tolerant receiver

Details High-voltage input tolerant receiver High-voltage input tolerant receiver

2005-10-18

2005-10-18

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S391000, C326S083000

Reexamination Certificate

active

06956412

ABSTRACT:
A high-voltage input tolerant receiver capable of achieving power savings with less distortion of analog signals is disclosed. When an external signal φC input from a PAD2is less than 3.6V, a p-channel MOS transistor P10is turned off. As a result, a control signal φE becomes 0V to turn on a p-channel MOS transistor P1.At this time, an intermediate signal φD output from a clamp circuit3becomes equivalent to the external signal φC, and is not distorted. However, when the external signal φC exceeds 3.6V, the p-channel MOS transistor P10is turned on, and a control signal φF output from a differential amplifier9becomes 0V. As a result, the p-channel MOS transistor P1is turned off, and a level keeper6is enabled. Since the level keeper6remains inactive until the external signal exceeds 3.6V, current flowing through the level keeper6can be reduced.

REFERENCES:
patent: 5966026 (1999-10-01), Partovi et al.
patent: 6441670 (2002-08-01), Coughlin et al.
patent: 6724226 (2004-04-01), Kim
patent: 6897688 (2005-05-01), Lee et al.
patent: 2000-278113 (2000-06-01), None

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