Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
1999-11-03
2001-09-04
Leja, Ronald W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
Reexamination Certificate
active
06285536
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high voltage input pad systems and methods and more particularly to electrostatic discharge protection for high voltage input pads.
2. Description of Related Art
The technical problems of interfacing semiconductor chips which operate with a 5 volt power supply with charge coupled devices (CCDs) have been inadequately addressed in the related art. In particular, the related art requires CCDs to operate from a 15 volt supply and to have an output signal with an offset of approximately 12 volts. Such systems with a standard ESD pad do not allow input voltages this large, because the input voltage range is limited to the value of the power supply range plus the voltage of two diode drops. In order to interface to an analog front end semiconductor chip which operates with a 5 volt power supply, the input CCD signal is AC-coupled through an external capacitor in order to reduce the input signal to a predetermined offset level. In one electrostatically discharge protected pad arrangement of the related art, the input signal pad is connected through resistor to an input amplifier. The resistor of this pad arrangement is in turn coupled to the connecting nodes of two pairs of first and second series-connected diodes which are coupled between ground potential and VDD. This circuit causes electrostatic discharge surges to be discharged through the first and second series-connected diodes either to ground or VDD. Thus, the voltage at a gate is prevented from getting much higher than VDD or much lower than ground. As a result, the voltage level of the gate outside of the semiconductor chip remains limited and prevents the chip from fusing and shorting to ground. This approach offers a certain level of electrostatic discharge protection in particular situations. The operating range of such input circuitry is, however, limited to a one diode drop below ground and one diode drop above VDD. This is an unacceptable input operating voltage range for many electric circuits without using an external AC coupling capacitor and systems which require ESD protection.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention, a circuit for protecting against the effects of electrostatic discharge includes a metal gate transistor (MGT) having a metal gate, a source connected to ground, and a drain; and first and second n-well resistors respectively connected to an input connection and an output connection for the circuit. With the pad ESD protection, voltage swings larger than the 5V supply can still couple to the amplifier through the internal AC coupling capacitor. This problem is solved as follows:
According to one embodiment of the present invention, an amplifier is protected from electrostatic discharge surges by connection of an anode grounded diode with its cathode connected to the input of the amplifier to handle negative surges, and in parallel therewith a bipolar junction transistor for diverting positive electrostatic surges to ground. According to one embodiment of the present invention, the base of the bipolar junction transistor is connected to the gate and drain of the higher potential one of a pair of series connected MOSFET transistors. According to one embodiment of the present invention, the lower potential one of the series connected MOSFET transistors is connected at its gate and drain to the source of the higher potential transistor and to the positive input connection of the amplifier. The protection circuitry according to the present invention thus protects camera semiconductor chips operating with a low voltage power supply from the detrimental effects of electrostatic discharge.
REFERENCES:
patent: 4605980 (1986-08-01), Hartranft et al.
patent: 4930036 (1990-05-01), Sitch
patent: 5545909 (1996-08-01), Williams et al.
patent: 5764464 (1998-06-01), Botker et al.
Holberg Douglas R.
Itani Nadi R.
Welland David R.
Bell Robert P.
Cirrus Logic Inc.
Leja Ronald W.
Lin Steven
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