Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-04-30
2003-04-08
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06545529
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a voltage generator for a semiconductor device.
2. Background of the Related Art
FIG. 1
illustrates an example of a conventional high voltage generating circuit described in U.S. Pat. No. 5,818,289. As illustrated therein, the conventional high voltage generating circuit includes oscillator
10
, clock signal generator
12
, pump circuit
14
and regulator
16
.
The oscillator
10
generates oscillation signal OSC used to trigger the operation of the clock signal generator
12
, and often is a ring oscillator initiated by enable signal EN. The clock signal generator
12
is triggered by the oscillation signal OSC to generate the clock signals used to control the operation of the pump circuit
14
. The pump circuit
14
is composed of multi stage charge pumps. The pump circuit
14
outputs the higher voltages needed for programming and erasing memory cells by performing a pumping operation according to the clock signals outputted from clock signal generator
12
.
The regulator
16
outputs reset signal RST used to turn the oscillator
10
off when the pump circuit
14
outputs the appropriate voltage. That is, the regulator
16
is used to control the operation of the oscillator
10
in order to cause the output of the pump circuit
14
to approach the desired output voltage. Thus, the oscillator
10
is turned on or off by the regulator
16
, which in turn affects the frequency of the clock signals produced by the clock signal generator
12
, to obtain the desired higher voltages from the pump circuit
14
.
FIG. 2
is a circuit diagram of the clock signal generator
12
. As illustrated in
FIG. 2
, flip-flop
220
outputs clock signals Ph
0
and Ph
0
# by dividing the oscillator signal OSC by two, and is reset by the reset signal RST. A plurality of logic gates are used to produce the desired clock signals (Ph
1
#, Ph
2
#, Ph
3
, Ph
1
a
, and Ph
2
a
) that control the operation of the pump circuit
14
upon receipt of the oscillation signal OSC and/or the output of the flip-flop
220
. Namely, inverters
231
and
232
provide the delays of the oscillation signal OSC that produce signal OSC-T.
NAND gate
234
and inverter
236
are used to produce clock signal Ph
1
by using signals Ph
0
and OSC-T. NAND gate
244
and inverter
246
are used to produce clock signal Ph
2
by using signals Ph
0
# and OSC-T. The clock signal Ph
1
is inverted by inverter
238
to produce clock signal Ph
1
#, and the clock signal Ph
2
is inverted by inverter
248
to produce clock signal Ph
2
#.
Inverters
240
and
242
are used to provide a delayed version of signal Ph
1
, which produces clock signal Ph
1
d
, and inverters
250
and
252
are used to provide a delayed version of signal Ph
2
, which produces clock signal Ph
2
d
. In addition, NOR gate
254
produces clock signal Ph
3
by NORing the oscillation signal OSC and the clock signals Ph
1
d
and Ph
2
d
. NAND gate
256
and inverter
258
produce clock signal Ph
1
a
by using the oscillation signal OSC and the clock signal Ph
1
d
, and NAND gate
260
and inverter
262
produce clock signal Ph
2
a
by using the oscillation signal OSC and the clock signal Ph
2
d.
FIG. 3
illustrates a circuit diagram of the pump circuit
14
controlled by clock signals (Ph
1
#, Ph
2
#, Ph
3
, Ph
1
a
, and Ph
2
a
). As illustrated in
FIG. 3
, the pump circuit
14
includes first and second pump stages
160
and
170
connected by charge transfer switch
80
. The input to first pump stage
160
may be either an input power supply voltage or the output from a previous pump stage. The output from second pump stage
170
provides the input to the next stage, or to an output stage if second pump stage
170
is the last in the charge pump.
The first pump stage
160
is composed of a switching transistor
60
, a capacitor
62
, a transistor
64
configured to act as a diode when the transistor
60
is switched “on,” and a pump capacitor
66
. Capacitors
68
and
69
represents the parasitic capacitance on the clock driver side associated with pump capacitors
66
and
67
, respectively, and capacitors
70
and
71
represents the parasitic capacitance on the charged nodes St
1
and St
2
, respectively.
Transistors
72
and
74
are used as clock drivers, and power supply voltage line
54
is used as the power source for transistors
74
and
75
. If the first pump stage is the first stage in the charge pump, the input supply voltage and the voltage of power supply line
54
are identical, that is, a VDD level. In addition, since the configuration of the second pump stage is the same as the first pump stage St
1
except for reference numerals, the detailed description thereof is omitted.
The operation of the pump circuit
14
will now be described using waveforms shown in FIG.
4
. At time t
1
, the clock signal Ph
1
# goes low, turning on the transistor
74
and thereby charging node S
1
P to the voltage level VDD of the power supply voltage line
54
. When node S
1
P is charged to the VDD level, the voltage of the node St
1
is increased by the pumping operation of the pump capacitor
66
and turns on the switching transistor
60
. As the result, node VG
1
is charged to an input supply voltage level through the turned-on switching transistor
60
. At time t
2
, the clock signal Ph
1
a
goes high, turning on the transistor
73
and thereby pulling node S
2
P down to a ground level.
At time t
3
, the clock signal Ph
1
# goes high, causing the transistor
74
to disconnect the node S
1
P from the power supply voltage line
54
. Soon after, the clock signal Ph
3
goes high, which causes charge transfer switch
80
to be turned on and connect the node S
1
P to the node S
2
P. Thus, for the next charging cycle, charge is transferred from the node S
1
P to the node S
2
P (i.e. from parasitic capacitor
68
to parasitic capacitor
69
). The amount of charge transferred will be one-half that stored in the capacitor
68
. Shortly prior to time t
4
, clock signal Ph
3
goes low to disconnect the node SIP from the node S
2
P.
At time t
4
, the clock signal Ph
2
# goes low, charging the node S
2
P to the power supply voltage. Thus, the switching transistor
61
is turned on according to the voltage of the node St
2
using the pumping operation of the pump capacitor
67
.
At time t
5
, the clock signal Ph
2
a
goes high, discharging the charge of the node S
1
P to the ground side through the transistor
72
, and increasing the voltage of the node VG
1
to an input supply voltage or more by means of the pumping operation of the capacitor
62
. As the result, the switching transistor
65
is turned on by the increased voltage of the node VG
1
, thereby providing the node St
1
and the node VG
2
with an input supply voltage without the threshold voltage drop.
At time t
6
, the clock signal Ph
2
# goes high, disconnecting the node S
2
P from the power supply voltage line
54
. Shortly after time t
6
, the clock signal Ph
3
goes high, turning on charge transfer transistor
80
and thereby connecting the node S
1
P to the node S
2
P. This has the effect of transferring charge from the node S
2
P to the node S
1
P (i.e. from capacitor
69
to capacitor
68
).
Shortly before time t
7
, the clock signal Ph
3
goes low again, disconnecting the node S
1
P from the node S
2
P. At time t
7
, the clock signal Ph
1
# goes low, connecting the node S
1
P to power supply voltage line
54
by means of transistor
74
. Thus, the voltage of node St
1
is pumped up to the level of an input supply voltage or more. Soon after time t
7
, the clock signal Ph
1
a
goes high, turning on the switching transistor
65
by the pumping of the capacitor
63
and thereby transferring the voltage of the node St
1
a
to the node St
2
. The voltage of the node St
2
is pumped by the pump capacitor
67
to be outputted using output transistor
77
, when the clock signal Ph
2
# goes high again.
In this way, i
Cunningham Terry D.
Fleshner & Kim LLP
Hynix / Semiconductor Inc.
Tra Quan
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