High voltage ESD protection circuit with low voltage...

Details High voltage ESD protection circuit with low voltage... High voltage ESD protection circuit with low voltage...

2006-04-11

2006-04-11

Leja, Ronald (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

07027276

ABSTRACT:
An ESD protection circuit includes a stacked NMOS transistor pair coupled between a pad and a negative voltage supply, with a first transistor's drain connected to the pad and a second transistor's source connected to the negative power supply. A first voltage divider provides reduced voltage from a high voltage positive power supply to a gate of the first transistor, a first diode string coupled between the gates of the first and second transistors, a second diode string with its anode coupled to the pad, an inverter with a source of its PMOS transistor coupled to a cathode of the second diode string and with its NMOS transistor coupled to the negative power supply, an output node of the inverter coupled to a gate of the second transistor, and a RC circuit coupled to an input node of the inverter, for dissipation of ESD current.

REFERENCES:
patent: 2003/0133237 (2003-07-01), Hung et al.
patent: 2004/0142527 (2004-07-01), Chen
patent: 2004/0233595 (2004-11-01), Ker et al.

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