High voltage ESD LDMOS-SCR with gate reference voltage

Details High voltage ESD LDMOS-SCR with gate reference voltage High voltage ESD LDMOS-SCR with gate reference voltage

2011-03-22

2011-03-22

Smith, Bradley K (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Bidirectional rectifier with control electrode

C257SE29040

Reexamination Certificate

active

07910950

ABSTRACT:
In an LDMOS-SCR ESD protection structure gate voltage of an ESD protection LDSCR is defined by connecting the gate to the source of a reference LDSCR. The reference LDSCR is implemented as a self-triggering device in which the snapback drain-source voltage (avalanche breakdown voltage) is controlled to be lower than that for the major LDSCR by adjusting the RESURF layer-composite overlap for the reference LDSCR to be different to that of the major LDSCR.

REFERENCES:
patent: 6137140 (2000-10-01), Efland et al.
patent: 6750515 (2004-06-01), Ker et al.
patent: 2001/0053581 (2001-12-01), Mosher et al.

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