High voltage ESD circuit by using low-voltage device with...

Details High voltage ESD circuit by using low-voltage device with... High voltage ESD circuit by using low-voltage device with...

2007-10-30

2007-10-30

Sherry, Michael (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

11269620

ABSTRACT:
An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit and a trigger current generating circuit. The trigger current generating circuit will generate trigger signal(s) to turn on the stacked MOS circuit under ESD stress condition. The ESD voltage can thus be discharged through the current path formed by the stacked MOS circuit. A lower trigger voltage is achieved by technologies disclosed, which will make an integrated circuit more sensitive to ESD.

REFERENCES:
patent: 5946177 (1999-08-01), Miller et al.
patent: 7221551 (2007-05-01), Chen

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