Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Patent
1995-10-23
1997-12-09
Callahan, Timothy P.
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
327379, 323315, H03K 1714
Patent
active
056964595
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to electronic amplifiers having a high-voltage output stage capable of a large output swing, a large transconductance and low quiescent power consumption.
BACKGROUND OF THE INVENTION
Many electronic systems utilize high voltage signals that exceed the 5 volts or less logic signal levels of typical digital systems. For example, applications such as communications systems that incorporate modems, serial line drivers, etc., may be required to operate at elevated voltage levels. In many flat panel displays, row and column electrodes are driven by integrated circuits (`ICs`) that must be capable of driving high voltages. Many types of nonvolatile semiconductor memories, e.g. EPROMs, EEPROMs and flash EEPROMs, require on-chip manipulation of high voltage signals in order to control programming. Implantable electronic medical devices, such as pacemakers, often require signal or output voltages in the range of 5 to 40 volts.
Typically, conventional monolithic high voltage amplifier circuits are fabricated in special CMOS processes that permit high voltage operation, since transistors fabricated in conventional low voltage CMOS processes normally break down at voltages around 6 to 10 volts. Transistor breakdown is due to phenomena such as zener breakdown of the drain, short channel effects and gate oxide failure. J. Y. Chen, CMOS Devices and Technology for VLSI, Prentice Hall, Englewood Cliffs, N.J., 1990; S. M. Sze, Semiconductor Devices Physics and Technology, John Wiley & Sons, New York, 1985. Double diffused drain structures, thicker oxides and long channel field effect transistors ("FETs") have been used in high voltage processes to achieve higher voltage breakdown levels. But these modifications result in characteristically larger transistors, i.e. a minimum transistor length greater than about 1.5 microns (.mu.m) as compared to less than 0.5 .mu.m for low voltage transistors. Larger transistors limit the integration density of the desired circuit functions.
Integrated circuits are generally fabricated with standard (also known in the art as "commodity") CMOS processes that are less expensive than specialty high voltage CMOS processes, but are only capable of reliably supporting voltages at or below 5 volts. Combining large, high voltage transistors with small, low voltage transistors on the same semiconductor substrate can be relatively expensive as a result of additional mask steps in the IC fabrication process. Therefore, specialty fabrication of conventional high voltage circuits raises the cost of manufacturing for applications that require extended voltage ranges.
Integrated circuits that implement high voltage circuitry using a low voltage fabrication process have been reported, but with limited applicability. In these circuits, high voltage n-FETs and p-FETs are fabricated by extending the drain terminal of the FETs with lightly doped parasitic implants. See Z. Parpia, C. A. T. Salama and R. A. Hadaway, `Modeling and Characterization of CMOS-Compatible High-Voltage Device Structures,` IEEE Transactions on Electron Devices, Vol. ED-34, No. 11, 1987, pp. 2335-2343; M. J. Declercq, M. Schubert and F. Clement, `5V-to-75V CMOS Output Interface Circuits,` Proceedings of the International Solid State Circuits Conference, San Francisco, 1993, pp. 162-163. These high voltage FETs have lightly doped drain-to-substrate diodes, which diodes for standard CMOS fabrication processes typically can sustain voltages of over 40 volts. These high voltage n-FETs and p-FETs can be used in operational amplifiers and buffer circuits with conventional transistor arrangements.
One of the problems the devices described by Parpia et al. and Declercq et al. have is that the gate oxide between the low voltage gate and the high voltage drain is a thin oxide, which cannot reliably withstand voltages above 5 volts for most small geometry CMOS processes. Fabricating high voltage devices using small device geometries (i.e. sub-micron transistor length) can degrade the transistor signifi
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Brunetti Jon
Neugebauer Charles F.
Steinbach Gunter
Arithmos, Inc.
Callahan Timothy P.
Shin Eunja
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