High-voltage dual-polarity I/O p-well pump ESD protection...

Details High-voltage dual-polarity I/O p-well pump ESD protection... High-voltage dual-polarity I/O p-well pump ESD protection...

2008-02-08

2009-12-15

Jackson, Stephen W (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

07633731

ABSTRACT:
An ESD protection circuit includes a discharge transistor formed in a p-well and having a drain coupled to the I/O pad, and a source coupled to ground. A MOS capacitor has a gate coupled to the I/O pad. A first resistor is coupled between the source and drain of the MOS capacitor and ground. A pulldown transistor has a drain coupled to the source and drain of the MOS capacitor, a source coupled to ground, and a gate coupled to a power-supply voltage node. A p-well control transistor has a source coupled to ground, and a drain coupled to the p-well. A second resistor is coupled between the I/O pad and the drain of the p-well control transistor. A pump transistor has a gate coupled to the gate of the discharge transistor, a drain coupled to the I/O pad, and a source coupled to the p-well.

REFERENCES:
patent: 5751507 (1998-05-01), Watt et al.
patent: 6690066 (2004-02-01), Lin et al.
patent: 6933567 (2005-08-01), Duvvury et al.
Duvvury, Charvaka et al., “Substrate Pump NMOS for ESD Protection Applications”, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000,11 pages, IEEE, New York, New York, USA.

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