Active solid-state devices (e.g. – transistors – solid-state diode – Tunneling pn junction device
Reexamination Certificate
2003-03-24
2004-08-03
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Tunneling pn junction device
C257S490000, C257S495000, C257S646000, C257S648000, C257S797000
Reexamination Certificate
active
06770917
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a high-voltage diode having a well-type zone of a first conductivity type, which is provided in a first main surface of a semiconductor body having a second conductivity type, being opposite to the first conductivity type. A metal contact is provided on the well-type zone. A rear side metallization is located, opposite to the metal contact, on a second main surface of the semiconductor body. The second main surface is located opposite to the first main surface and an edge termination with a channel stopper is provided. A passivation layer, which is provided on the first main surface in a region between the metal contact and the channel stopper, covers a pn junction issuing at the first main surface.
To date, high-voltage diodes, which are provided for relatively high voltages of, in particular, above about 400 V, have been provided, and use planar structures, with edge terminations containing field plates, field rings, dielectric insulating layers, semi-insulating coverings and a varying doping in the edge region. In this case, these measures are employed individually or in combination, it perfectly well being the case that, by way of example, field plates, field rings and dielectric insulating layers are also used jointly.
In this case, it has been shown that, during the fabrication of the diode, even more steps are necessary for an edge termination that satisfies the requirements made of it than for setting the desired on-state and switching properties. Thus, by way of example, diode edges based on field plates require relatively complicated fabrication processes.
Specifically, in the reference by C. Mingues and G. Charitat, titled “Efficiency of Junction Termination Techniques vs. Oxide Trapped Charges”, 1997 IEEE International Symposium on Power Semiconductor Devices and ICs, Weimar, pages 137 to 140, edge terminations with field rings, semi-insulating layers or a junction termination extension (JTE) are compared with one another especially with regard to their sensitivity to oxide charges. In this case, the use of SIPOS techniques is recommended as semi-insulating layers for high-voltage applications.
European Patent EP 0 341 453 B1, corresponding to U.S. Pat. No. 4,954,868, discloses a MOS semiconductor component for a high reverse voltage, in which field plates are disposed on insulating layers of different thicknesses. In this case, some of the field plates serve as channel stoppers. In diodes, such field plates used as channel stoppers are often connected to the rear side potential of the diode by a p-conducting region in the edge region, even though a connection via an n-conducting region would inherently be more advantageous because a p-conducting channel could thereby be reliably prevented. However, given an otherwise customary fabrication process, an additional mask step would be necessary for such a connection via an n-conducting region.
When sawing a wafer into individual chips, so-called chipping stoppers are intended to prevent crystal defects from propagating from the sawing edge into the active region of the respective chips. The chipping stoppers are usually realized by a field oxide between the functional edge region of the chip and the sawing line.
If pn junctions having a high blocking capability are only covered with dielectric passivation layers, then under the action of external charges which are attributable for example to moisture, alkaline or metallic contamination, etc., changes in the long-term blocking stability can be observed in the event of blocking loading of the pn junction. These changes are brought about by a drift of ionic charges in the electric field of the reverse-biased pn junction on or in the passivation layer. Depending on the sign of the ionic charges and also depending on the structure of the edge termination, that is to say depending on the so-called edge contour, the ionic charges can lead to an increase or to a decrease in the blocking capability of the pn junction. In the case of a diode with a p-conducting anode, in this case, as the doping in the n-conducting base decreases and therefore as the bulk blocking capability of the diode increases, as a result of a greater induction effect, the influence of such surface charges in and on the passivation layer increases, which leads to a dramatic increase in the risk of blocking instabilities. In this connection, reference should be made to the so-called Yoshida effect; when using insulator layers for passivation, a drift in the reverse voltage is occasionally observed on account of an injection of hot electrons during the on-state loading when changing over to the blocking state of the pn junction.
By using semi-insulating layers directly on the pn junctions, the influence of such surface charges can be suppressed given suitable settings of the layer and interface parameters, such as, for example, of the layer thickness and doping of the semi-insulating layers. The semi-insulating layers which are currently used for the passivation of pn junctions contain, for example, amorphous silicon (a-Si) or hydrogen-doped amorphous carbon (a-C:H), as are described in European Patents EP 0 400 178 B1 and EP 0 381 111 B1 (corresponding to U.S. Pat. No. 5,039,358). With these semi-insulating layers, parasitic effects, such as an elevated reverse current or the formation of inversion layers, can be avoided given corresponding optimization of the amorphous-crystalline heterojunctions between the layers and the electrically active silicon substrate. Moreover, semi-insulating passivation layers can actively build up image charges by virtue of their finite state density and thus shield extraneous charges that penetrate externally, and also dissipate injected charge carriers by virtue of their finite specific conductivity. Overall, a semi-insulating passivation thus leads to a significantly improved long-term stability compared with a dielectric passivation.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a high-voltage diode and a method for fabricating the high-voltage diode that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which has a rating for reverse voltages of, in particular, above about 400 V and preferably above about 500 V, and can be fabricated with the least possible process complexity and thus a small number of photo technologies and, in the edge region, can readily be equipped with a channel stopper for avoiding leakage currents and a chipping stopper for limiting the extent of saving defects; moreover, the intention is to provide a method for fabricating such a high-voltage diode.
With the foregoing and other objects in view there is provided, in accordance with the invention, a high-voltage diode. The diode contains a semiconductor body having a first main surface and a second main surface disposed opposite the first main surface, the semiconductor body is formed of a second conductivity type being opposite to a first conductivity type. A well-type zone of the first conductivity type is disposed in the first main surface of the semiconductor body. A metal contact is disposed on the well-type zone. A rear side metallization is disposed on the second main surface of the semiconductor body and disposed opposite to the metal contact. An edge termination having a channel stopper is provided. A passivation layer is disposed on the first main surface in a region between the metal contact and the channel stopper. The passivation layer covers a pn junction issuing at the first main surface. The passivation layer contains an amorphous carbon doped with hydrogen or an amorphous silicon and serves as a chipping stopper in a region of the semiconductor body outside the channel stopper. At least one edge is provided as an alignment structure disposed in the first main surface in a region of the well-type zone.
The measures of producing the masking insulating layer on the semiconductor body and the patterning of the mask insulating lay
Barthelmess Reiner
Mauder Anton
Pfirsch Frank
Schmidt Gerhard
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Loke Steven
Stemer Werner H.
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