Active solid-state devices (e.g. – transistors – solid-state diode – With specified shape of pn junction
Reexamination Certificate
2002-03-28
2002-11-12
Nibbling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
With specified shape of pn junction
C257S051000, C438S558000, C438S489000, C438S537000, C438S540000, C438S541000
Reexamination Certificate
active
06479885
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to electrical components and, more particularly, to semiconductor devices constructed to perform reliably at high voltages.
BACKGROUND
Various types of semiconductor devices are known in the art. Such devices include diodes and transistors at a relatively simple level, and complex integrated circuits and microprocessors at a relatively advanced level. Such semiconductor devices typically perform at low voltages, for example 5 Volts (V), and are therefore usually immune to problems associated with high voltages across electrical components. Accordingly, such devices have appreciable durability, dependability and performance characteristics at low voltages whereby they have come to be utilized extensively in low voltage circuits. Additionally, such semiconductor devices are relatively inexpensive to manufacture which further contributes to their desirability for commercial use.
At higher voltages, however, such devices are prone to damage and failures. For example, a diode constructed by any one of the known ways in the art and implemented in an ordinary 5V circuit may have an impeccable performance record over a significant number of years. Another diode constructed substantially identically but proportionally scaled to larger dimensions for use in a higher voltage circuit, for example 2 kilovolts (KV), and implemented therein may fail within the initial few hours of use at such high voltage. Although such failure may be due to any of the various hazards associated with the magnitude of electrical power and electrical field strengths generated at such high voltages, such failure in semiconductor components typically occurs due to the electrical fields generated by the current flowing therethrough at the edge terminations of the P/N junctions thereof. Such failure is sometimes termed as snapback in the art. Upon snapback, the operational parameters of the semiconductor component typically fall from 2KV to 0V, whereby the semiconductor component is essentially reduced to a resistor. In such event, the component, and on occasion the entire circuit, must be replaced in order to regain an operational circuit or device.
Given the reliability and success of semiconductor components in low voltage circuits of commonly used devices such as cellular phones, laptop computers, portable audio equipment, and so forth, there is a recognized need to implement similar components for performing similar tasks in higher voltage circuits of devices such as televisions and the like. Recent advancements in high definition television technology, for example, require diodes rated at 1.75KV or higher. However, diodes currently available are rated at only about 1.5KV. Some diodes are rated at 1.7KV; however, they do not provide high performance at elevated temperatures. As a result, manufacturers of such high voltage devices test for and choose the best diodes of the available 1.5KV diodes, and use them in 1.75KV applications. Expectedly, the failure rate of such diodes is higher than desirable, and furthermore the procedure of testing for the best diodes from a lot of 1.5KV diodes imposes an unnecessary additional cost upon the manufacturing process for such devices.
Accordingly, there is a need for diodes rated higher than 1.5KV, particularly diodes rated at 1.75KV or higher, which perform reliably at such high voltages, which are substantially immune from the possibility of snapback at such high voltages, which are relatively inexpensive to manufacture, and which do not need to be tested and screened for selecting only the best diodes.
The present invention is directed to overcoming one or more of the problems set forth above. These and other advantageous features of the present invention will be in part apparent and in part pointed out herein below.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a plurality of electrical semiconductor components are constructed for use in high voltage applications. A substrate layer is formed by a crystalline growth method known in the art to form an ingot which is sliced to a desired thickness of the substrate layer. A second layer, preferably an epitaxial layer, is then deposited onto or formed in a surface of the substrate layer. The substrate layer in a preferred embodiment is a P
+
layer preferably formed from silicon material, and the epitaxial layer is an N
−
layer preferably formed from silicon material as well.
In a preferred embodiment, a layer containing phosphorous is deposited on the surface of the epitaxial layer. The phosphorous layer is then masked whereby preferably only the edges of individual devices to be cut therefrom remain exposed, and the exposed edges are etched away by any one of the various methods known in the art thereby leaving an array of phosphorous patches remaining at substantially the middle portions of the individual devices on their respective surfaces of the epitaxial layer. The device is then heated to a temperature preferably in the range from between 1,000° C. and 1,300° C., whereby a portion of the phosphorous material diffuses with the epitaxial layer of each individual device. The depth of the diffusion region will be deeper directly adjacent to, or beneath, each patch of phosphorous, and will be comparatively shallower at the edges thereof, that is, at the edges of each individual device. The temperature to which the device is heated and the duration thereof controls the amount of diffusion of the phosphorous into the epitaxial layer. Subsequent to the diffusion step, the remaining diffusion source patches are removed, which may be done by any conventional method or process known in the art.
By virtue of the phosphorous diffusion, a portion of the epitaxial layer of each individual device becomes a doped N
+
-type semiconductor. The junction between the N-type epitaxial layer and the P-type conductive type substrate layer provides a P/N junction. Each individual device may then be cut away for use in an electrical circuit. During use of a device thus constructed, a majority of the flow of current occurs substantially through the middle portion of the device because of the deeper diffusion region in the middle. Comparatively, the magnitude of the electric field at the edges is lower due to the shallower diffusion region. Utilizing such a device in a high voltage application will, therefore, help minimize the possibility of snapback at the edges of the device, thereby improving the reliability and utility of such a device in high voltage applications.
In another preferred embodiment of the present invention, a P
+
epitaxial layer may be grown on an N
−
substrate layer. In this particular embodiment, instead of depositing the dopant material on the epitaxial layer, a layer of the N-type dopant material, such as phosphorous, is deposited upon the opposite surface of the N-type substrate layer and the dopant material is then masked and etched to form patches as described above. Heating the devices, as again previously described, will form similar diffusion regions in the area of the respective patches. The remaining dopant material is thereafter removed and individual devices may be cut away from the remaining semiconductor.
In yet another embodiment of the present invention, instead of depositing a layer containing dopant material onto the epitaxial layer as described above, masking the dopant material layer, and etching away the exposed portions thereof, the dopant material layer is masked at the application step to achieve the desired pattern. In other words, a layer of dopant containing material is screen printed upon the epitaxial layer in an array of diffusion source patches that are substantially identical to the array of diffusion source patches remaining after the etching step described above. The remaining steps of heating, creating a diffusion layer, and removing the remaining amount of dopant containing material in the diffusion source patches may be implemented similarly as described above. This process is an improvement
Buchanan Walter R.
Hamerski Roman J.
Blackwell Sanders Peper Martin LLC
Elliott Kyle L.
Fab-Tech Inc.
Nibbling John F.
Simkovic Viktor
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