Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1995-12-27
2001-01-30
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S078000, C327S205000, C327S206000, C327S437000, C326S112000
Reexamination Certificate
active
06181172
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuits and, more particularly, to techniques for reducing high voltage stress on the transistors of a high-voltage detector circuit which distinguishes, for example, between 13 volts and 6 volts.
2. Prior Art
Voltage stress on the gate oxide of an integrated-circuit transistor produces long-term degradation of the transistor. It has been found that an electric field in the range of 7 to 10 Megavolts per centimeter across a gate-oxide causes charge to be injected into the gate oxide. This injected charge causes long term degradation of the transistor, such as, for example, threshold voltage variations, variations in mobility, etc.
An example of a circuit in which the gate oxide of a transistor is stressed by high voltage is a detector circuit which is used to detect the presence of a 13 volt programming voltage used for programming an array of anti-fuse memory circuits. The detector circuit can have 13 volts across the gate oxide of a detector transistor. For a gate oxide thickness of 165 Angstroms and a voltage of 13 volts, an electric field of 7.88 MegaV/cm is generated between the top of the gate and the substrate of the transistor. An electric field of this magnitude is within the range where long-term degradation occurs.
FIG. 1
is a circuit diagram
100
of a prior art high voltage detection circuit
100
for detecting the presence of a 13 volt programming voltage or a 6 volt supply voltage. This circuit is designed to discriminate between a 13 volt signal or a 6 volt signal provided at an input terminal
102
. The input terminal
102
is connected to the drain and source terminals of NMOS transistor
104
. A substrate terminal for NMOS transistor
104
is connected to a ground reference voltage. The source terminal of the transistor
104
is connected to the source and substrate terminals of a PMOS transistor
106
. The gate terminal of the PMOS transistor
106
is connected to VCC and to the gate terminal and the drain terminal of another NMOS transistor
108
. The source terminal of PMOS transistor
106
is connected to the source terminal of NMOS transistor
108
. The drain terminal of the PMOS transistor
106
is connected to a drain terminal of a NMOS bleeder transistor
110
and to an output terminal
112
. The source terminal of the NMOS bleeder transistor
110
is connected to a ground reference voltage. The gate terminal of the NMOS bleeder transistor
110
is connected to VCC. The NMOS bleeder transistor
110
provides a fixed resistance to ground for draining charge on the output terminal
112
to ground when 6 volts appears at the input terminal
102
. In operation, a 13 volt signal on terminal
102
causes a logical high voltage to appear on output terminal
112
. A 6 volt signal on terminal
102
causes a logical low voltage to appear on output terminal
112
.
A problem with the voltage detection circuit
100
of
FIG. 1
is that 13 volts can appear across the gate oxide of NMOS transistor
104
between the gate terminal and the substrate terminal. The thickness of the gate oxide of transistor
104
can range between 165 to 185 Angstroms. With 13 v and 165 Angstroms, the field across the gate oxide of transistor
104
is 7.88 MegaV/cm between the top of the gate and substrate. An electric field in the range of 7 to 10 MegaVolts per centimeter causes charges to be injected into the gate oxide resulting in a long term degradation of the transistor.
Consequently, a need exists for a voltage detector circuit which can discriminate between a 13 v programming voltage and a 6 v voltage without creating a field across the gate oxide of a sensing transistor in excess of 7.0 MegaV/cm.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a circuit which can discriminate between a 13 v programming voltage and a 6 v voltage without creating a field across the gate oxide of a sensing transistor in excess of 7.0 MegaV/cm.
In accordance with this and other objects of the invention, a voltage detector circuit is provided which can discriminate between a 13 v programming voltage and a 6 v voltage without creating a field across the gate oxide of a sensing transistor which is in excess of 7.0 MegaV/cm. An input terminal is provided with a two-level input signal. The first level of the input signal is a high voltage (13 volts) and the second level is a VCC or 6 v voltage level.
A PMOS transistor has a source terminal and a substrate terminal, both connected to the input terminal. The PMOS transistor has a gate terminal connected to the VCC voltage level, and the PMOS transistor has a drain terminal. The gate to bulk voltage across the PMOS transistor does not exceed the input voltage minus VCC.
A shunt NMOS transistor has a drain terminal connected to the drain terminal of the PMOS transistor and a source terminal connected to a ground terminal. A gate terminal of the shunt NMOS transistor is connected to the VCC voltage level. The NMOS transistor is turned on to provide a shunt resistance between the drain terminal of the PMOS transistor and ground.
A series NMOS transistor has a drain terminal connected to the drain terminal of the PMOS transistor and has a source terminal. A gate terminal of the series NMOS transistor is connected to VCC.
A Schmitt trigger circuit is connected to the source terminal of the series NMOS transistor to restore signal levels to full voltage levels.
A semiconductor circuit structure is provided which discriminates between a high voltage input signal and a lower voltage input signal without creating an excessive field across the gate oxide of a sensing transistor. The structure includes a p
−
substrate and a n
−
well formed in the p substrate. An n
+
input-connection region is formed in the n
−
well. A first p
+
region and a second p
+
region are both formed in the n
−
well to define a PMOS transistor region or channel there between the two gate p
+
regions. A gate oxide is formed adjacent to the channel and a gate contact is formed over the gate oxide layer. The gate contact is connected to a gate terminal. A detector input terminal is connected to the n
+
input connection region and the first p
+
source region. An output terminal connected to the second p
+
region drain.
REFERENCES:
patent: 4862019 (1989-08-01), Ashmore, Jr.
patent: 5118968 (1992-06-01), Douglas et al.
patent: 5510735 (1996-04-01), Mahabadi
King Patrick T.
Le Dinh T.
Philips Electronics North America Corp.
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