High voltage depletion mode MOS power field effect transistor

Details High voltage depletion mode MOS power field effect transistor High voltage depletion mode MOS power field effect transistor

1986-07-24

1988-11-22

Edlow, Martin H.

357 238, 357 45, H01L 2978, H01L 2710

Patent

active

047869526

ABSTRACT:
A vertical depletion mode power field effect transistor having a greatly increased drain-to-source breakdown voltage. The drain region is formed in the substrate and separated from the channel by a first insulative layer having apertures which allow the passage of electrical currents. The channel, which is formed between the first insulative layer and a second insulative layer parallel to the substrate surface, contains both a source region, formed by implantation of impurities of the same type as are used to form the drain region, and a gate region. In this configuration, the normally high voltage which exists between the gate and drain is imposed over a greater distance than in conventional depletion mode vertical FETs, so that this new configuration produces vertical power FETs having much higher breakdown voltages than do conventional depletion mode vertical FETs. Islands having a conductivity type opposite to that used to form the source region are formed immediately below the second insulative layer and serve to prevent the creation of a charge inversion layer in the channel, where the inversion layer adversely affects the turn off characteristic of the j-MOS power transistor.

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