High voltage CMOS technology with N-channel source/drain extensi

Details High voltage CMOS technology with N-channel source/drain extensi High voltage CMOS technology with N-channel source/drain extensi

1983-02-23

1986-05-27

Hearn, Brian L.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29577C, 29578, 148 15, H01L 21265, H01L 2176

Patent

active

045906637

ABSTRACT:
N-channel devices are fabricated with lightly doped drain/source extensions in a CMOS process, without the requirement of an extra mask level. A merged mask technique uses an oversized version of the N-channel gates, expanded by two alignment tolerances per side, combined with the regular N+ source/drain mask. The oversized gate photoresist prevents the heavy N+ source/drain implant from counterdoping the previously introduced lightly doped drain blanket implant. In the P-channel regions the N-type LDD extensions are counterdoped by the regular P+ source/drain implant. This high-voltage process provides 20 V parts with 4 micron geometries, scalable to other voltages.

REFERENCES:
patent: 4356623 (1982-11-01), Hunter
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4406049 (1983-09-01), Tam et al.
patent: 4419809 (1983-12-01), Riseman et al.
patent: 4442591 (1984-04-01), Haken
Ogura et al., "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate FET", IEEE Trans., vol. ED-27, No. 8, Aug. 1980.

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