High-voltage CMOS process

Details High-voltage CMOS process High-voltage CMOS process

1984-01-12

1986-09-23

Hearn, Brian E.

Metal treatment

Stock

Ferrous

357 2311, 357 52, 29571, 29578, 29576B, 148 15, 148188, H01L 2978, H01L 21265, H01L 2176

Patent

active

046138854

ABSTRACT:
A high-voltage CMOS process, providing (for 5 micron geometries) both field thresholds and junction breakdowns in excess of 20 volts, wherein only one channel stop implant is used. A double-well process in an epitaxial structure is used. Phosphorus is preferably used as the dopant for the N-tank, and boron is used for the blanket channel stop implant. The boron tends to leach into oxide, and the phosphorus tends to accumulate at the surface, and a high field threshold is achieved over both PMOS and NMOS regions.

REFERENCES:
patent: 3956035 (1976-05-01), Herrmann
patent: 3983620 (1976-10-01), Spadea
patent: 4013484 (1977-03-01), Boleky et al.
patent: 4135955 (1979-01-01), Gasner et al.
patent: 4223334 (1980-09-01), Gasner et al.
patent: 4277291 (1981-07-01), Cerofolini et al.
patent: 4385947 (1983-05-01), Halfacre et al.
patent: 4391650 (1983-07-01), Pfeifer et al.

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