High voltage CMOS output buffer constructed from low voltage...

Details High voltage CMOS output buffer constructed from low voltage... High voltage CMOS output buffer constructed from low voltage...

2011-01-04

2011-01-04

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C326S081000

Reexamination Certificate

active

07863962

ABSTRACT:
A high voltage CMOS output buffer is constructed from low voltage CMOS transistors. The output buffer employs a series of unique CMOS inverter stages, each of which contains a switched PMOS transistor, one or more voltage drop blocks, and a switched NMOS transistor. The voltage drop blocks are composed of stacked PMOS transistors that are diode-connected—i.e., the PMOS gate terminal is connected to the PMOS drain terminal, and the PMOS body (N-well) terminal is connected to the PMOS source terminal. The diode-connected PMOS transistors reduce the voltage across the transistor gate oxide to a safe value, for all internal PMOS/NMOS transistors inside the CMOS output buffer.

REFERENCES:
patent: 5378943 (1995-01-01), Dennard
patent: 5537059 (1996-07-01), Asahina
patent: 6664823 (2003-12-01), Yokoi

Affiliated with

Also associated with

Rating

High voltage CMOS output buffer constructed from low voltage... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High voltage CMOS output buffer constructed from low voltage..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High voltage CMOS output buffer constructed from low voltage... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2644106