Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-03-05
2001-01-23
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06177830
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to a memory array architecture for standard sub 0.35 micron processes.
2. Description of the Related Art
Most integrated circuits (“chips”) now in use are fabricated in what is called CMOS (complementary metal oxide semiconductor) technology, which forms both PMOS and NMOS transistors in a silicon substrate. One of the main objectives of integrated circuit technology is to minimize transistor size. Typically, transistors are described in terms of their minimum feature dimension. Current technology provides a minimum feature size of 0.35 &mgr;m or less. The minimum feature size, which is also referred to as a “line width”, refers to the minimum width of a transistor feature such as the gate width, or the separation between source and drain diffusions. Typically, 0.35 &mgr;m technology is used to form CMOS transistors having a gate oxide thickness of 70 Å. A
0.18 _&mgr;m technology is used to form CMOS transistors having a gate oxide thickness of
40 Å. The gate “oxide”, actually a silicon dioxide layer, is the electrically insulating (dielectric) layer interposed between the conductive gate electrode, which is typically a polycrystalline silicon structure formed overlying the principal surface of the silicon substrate in which the integrated circuit is formed, and the underlying silicon which typically is the channel portion of the transistor extending between the source and drain regions. Transistors of
0.35 _&mgr;m size typically operate at a voltage of
3.3 Volts. Transistors of
0.18 _&mgr;m size typically operate at a voltage of
1.8 Volts. Greater voltages are likely to destroy the transistor by rupturing the gate oxide.
In the field of data storage, there are two main types of storage elements. The first type is a volatile storage element such as typically used in DRAM (dynamic random access memory) or SRAM (static random access memory) in which the information stored in a particular storage element is lost the instant that power is removed from the circuit. The second type is a non-volatile storage element in which the information is preserved even if power is removed. Typically, the types of transistor devices used to provide non-volatile storage are substantially different from those used in ordinary logic circuitry or in volatile storage, thereby requiring different fabrication techniques. Hence, if non-volatile storage is included on an integrated circuit fabricated using conventional CMOS technology, chip size and complexity are undesirably increased.
Thus, heretofore it has not possible to include non-volatile storage on a integrated circuit chip formed exclusively using standard CMOS processes.
SUMMARY
Accordingly, the present invention provides a non-volatile memory circuit which is fabricated using a standard sub 0.35 micron CMOS process. In one embodiment, the non-volatile memory circuit is fabricated using a standard 0.18 micron CMOS process. The core transistors fabricated in accordance with the 0.18 micron &mgr;m CMOS process have a gate oxide thickness of 40 Å, and are designed to operate in response to a nominal supply voltage of 1.8 Volts. The 0.18 micron CMOS process also provides for the fabrication of high voltage CMOS transistors that have a gate oxide thickness of 70 Å. These high voltage CMOS transistors are typically used in the input/output (I/O) circuitry of the integrated circuit chip.
The present invention includes a non-volatile memory cell that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. Advantageously, the high voltage p-channel transistor has a higher breakdown voltage than a high voltage n-channel transistor having the same size. As a result, a relatively high programming voltage can be provided through the high voltage p-channel transistor, without damaging the p-channel transistor.
In one embodiment, the state of the low voltage storage transistor is read through the p-channel transistor. In another embodiment, the state of the low voltage storage transistor is read through a high voltage n-channel transistor.
The present invention also includes a decoder circuit for applying bit line and/or word line control voltages to a non-volatile memory cell. In accordance with one embodiment, the decoder circuit includes a first pair of high voltage p-channel transistors coupled in series between a programming voltage supply and the control line, and a second pair of high voltage p-channel transistors coupled in series between the V
CC
voltage supply and the control line. The first pair of high voltage p-channel transistors are turned on to couple the programming voltage to the control line, and the second pair of high voltage p-channel transistors are turned on to couple the V
CC
voltage supply to the control line. The relatively high breakdown voltages of the high voltage p-channel transistors advantageously prevent damage to these transistors during operation of the decoder circuit.
In one variation, the decoder circuit can additionally include a pair of high voltage n-channel transistors coupled in series between the control line and a ground voltage supply. In this variation, the pair of n-channel transistors are turned on to couple the ground voltage supply to the control line.
The present invention also includes a charge pump circuit for generating the high programming voltage in response to a clock signal (and the complement of the clock signal). In one embodiment, the charge pump circuit includes a first set of high voltage p-channel transistors connected to operate as capacitors, and a second set of high voltage p-channel transistors connected to operate as capacitors. During a first half cycle of the clock signal, the first set of capacitor-coupled p-channel transistors are charged, and the second set of capacitor-coupled p-channel transistors is discharged. During a second half cycle of the clock signal, the second set of capacitor-coupled p-channel transistors are charged, and the first set of capacitor-coupled p-channel transistors is discharged. The relatively high breakdown voltage of the capacitor-coupled p-channel transistors enables these transistors to withstand the high programming voltage generated by the charge pump circuit.
Another embodiment of the present invention includes a system-on-a-chip structure that implements the non-volatile memory of the present invention.
The present invention will be more fully understood in view of the following description and drawings.
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Ying Shi; T. P. Ma; Sharad Prasad; an Sumit Dhanda, “Polarity Dependent Gate Tunneling Currents in Dual-Gate CMOSFET's”, IEEE Transactions on Electron Devices, vol. 45, No. 11, Nov. 1998, pp. 2355-2360.
Bever Hoffman & Harms LLP
Cartier Lois D.
Cunningham Terry D.
Hoffman E. Eric
Tra Quan
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