High voltage charge pump for providing output voltage close...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Details

C327S537000, C363S060000

Reexamination Certificate

active

06466079

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a charge pump circuit for generating a voltage on an integrated circuit device. More specifically, the present invention relates to an output stage for a charge pump circuit that provides a DC voltage output that approaches the maximum high (breakdown) voltage of a CMOS device.
BACKGROUND OF THE INVENTION
FIG. 1
is a block diagram of a conventional voltage generator
100
used to generate a DC voltage, greater than the V
CC
supply voltage, on an integrated circuit chip. Voltage generator
100
includes synchronizer
101
, charge pump
102
and output stage
103
. Synchronizer
101
provides a clock signal CLK having a frequency of F
CLK
to charge pump
102
. In response, charge pump
102
generates a charge pump output voltage V
CH
having an amplitude of V
CH

MAX
and a frequency of F
CLK
. Also in response to the CLK signal, charge pump
102
provides a switching signal V
SW
having a frequency of F
CLK
. The V
CH
and V
SW
signals are provided to output stage
103
.
Output stage
103
includes NMOS transistor
111
, capacitor
112
and output terminal
113
. The source of NMOS transistor
111
is coupled to receive the V
CH
signal, the gate of NMOS transistor
111
is coupled to receive the V
SW
signal, and the drain of NMOS transistor is coupled to output terminal
113
. The bulk of NMOS transistor
111
is coupled to ground. Capacitor
112
is coupled between the drain of NMOS transistor
112
and ground. The output voltage V
OUT
is provided on output terminal
113
.
Voltage generator
100
operates as follows. Shortly after the V
CH
signal transitions to a high state, the V
SW
signal transitions to a high state, thereby turning on NMOS transistor
111
and charging capacitor
112
. The V
SW
signal subsequently transitions to a low state, thereby turning off NMOS transistor
111
. Shortly thereafter, the V
CH
signal transitions to a low state. At this time, capacitor
112
discharges. Capacitor
112
ensures that a relatively constant DC output voltage V
OUT
is provided on output terminal
113
.
The maximum output voltage V
OUT
is undesirably limited by the characteristics of NMOS transistor
111
. NMOS transistor
111
has a maximum high voltage V
MAX
(i.e., breakdown voltage) that cannot be exceeded, or the transistor will be damaged. The maximum output voltage V
OUT
is equal to the breakdown voltage V
MAX
minus the threshold voltage of transistor
111
(V
TH
) and the body effect. Thus, if the maximum voltage V
MAX
of NMOS transistor
111
is 12 Volts, and the threshold voltage V
TH
and body effect of NMOS transistor
111
is 2 Volts, then the output voltage V
OUT
is limited to only 10 Volts.
Note that NMOS transistor
111
cannot simply be replaced by a PMOS transistor because the source-to-bulk junction and the drain-to-bulk junction of the PMOS transistor would become forward biased. thereby preventing proper charging and discharging of capacitor
112
.
It would therefore be desirable to have a voltage generating circuit that is capable of overcoming the deficiencies of the above-described circuit.
SUMMARY
Accordingly, the present invention provides a voltage generation circuit having an improved output stage, which allows the maximum output voltage to closely approximate the breakdown voltage of a CMOS transistor.
An output stage of the present invention includes a first PMOS transistor having a source region and a bulk region coupled to receive the charging voltage signal V
CH
from a corresponding charge pump. The charging voltage V
CH
periodically transitions between a low charging voltage V
CH

MIN
and a high charging voltage V
CH

MAX
. The first PMOS transistor further includes a drain region coupled to a first node, and a gate coupled to receive a switching voltage signal V
SW
.
A second PMOS transistor is connected in series with the first PMOS transistor. More specifically, the second PMOS transistor includes a drain region coupled to the first node, a gate coupled to receive the switching voltage signal V
SW
, and a source region and a bulk region coupled to an output terminal.
A capacitor is coupled between the output terminal and the ground voltage supply terminal. This capacitor charges and discharges to provide an output voltage V
OUT
. A pull-up transistor can be provided to help pull the output terminal up toward a voltage equal to a V
CC
supply voltage minus the threshold voltage of the pull-up transistor.
A discharging transistor is coupled between the first node and a ground voltage supply terminal. The gate of the discharging transistor is coupled to receive a discharge enable signal (DIS) from the charge pump. In one embodiment, the discharging transistor is an NMOS transistor.
During a first period of a charging cycle, the charging voltage V
CH
is asserted at the high value of V
CH

MAX
, and the switching voltage V
SW
is asserted low, such that the first and second PMOS transistors are turned on, and the capacitor charges. The first PMOS transistor is sized to have a relatively high on-resistance compared to the second PMOS transistor. As a result, the charging current is minimized, thereby minimizing the drain-to-source voltage drop across the second PMOS transistor to a voltage less than a junction voltage drop. Consequently, the drain-to-bulk junction of the second PMOS transistor is not forward biased during the first period of the charging cycle. The first and second PMOS transistors enable the voltage applied to the capacitor to be approximately equal to V
CH

MAX
. As a result, the output voltage V
OUT
can advantageously approach the breakdown voltage of the PMOS transistors.
During a second period of the charging cycle, the discharge enable signal DIS is asserted high, thereby turning on the discharging transistor coupled to the first node, and causing the first node to discharge. Because the drains of the first and second PMOS transistors are coupled to the first node, the drain-to-bulk junctions of the first and second PMOS transistors are prevented from being forward biased during the second period of the charging cycle.
The present invention will be more fully understood in view of the following description and drawings.


REFERENCES:
patent: 4593320 (1986-06-01), Nishizawa et al.
patent: 5352936 (1994-10-01), Allen
patent: 5506528 (1996-04-01), Cao et al.
patent: 6184594 (2001-02-01), Kushnarenko

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