Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1998-07-20
2001-02-13
Carroll, J. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S535000
Reexamination Certificate
active
06188121
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a high voltage capacitor. In particular, the invention relates to a high voltage capacitor adapted to be integrated monolithically on a semiconductor substrate accommodating a field oxide region overlaid by a first layer of polycrystalline silicon isolated from a second layer of polycrystalline silicon by an interpoly dielectric layer.
BACKGROUND OF THE INVENTION
Background Art
As is well known, many applications related to semiconductor integrated electronic circuits require the use or generation of higher voltages than a supply voltage Vcc. In particular, electrically programmable non-volatile memories, such as EPROMs, EEPROMs, or FLASH EEPROMs, need a write voltage far above the standard 3 to 5 Volts supply.
The most up-to-date integrated circuit applications concern systems which utilize supply voltages in the 3-Volt range. Such systems often employ semiconductor memories of the non-volatile type. In order to maintain the characteristics of such active integrated devices as transistors or memory cells unchanged at low supply voltages, it has been necessary to introduce thin (160Å or less) oxides.
However, it is a well recognized fact that EPROMs, EEPROMs and FLASH EEPROMs all require high (12V) programming voltages that such thin oxides cannot withstand. Thus, the introduction of a second and thicker (e.g. 20 to 30 nm) oxide has become necessary for high voltage transistors. These programming voltages must, in the instance of EEPROMs and FLASH EEPROMs, be generated internally from the external supply voltage by means of suitable circuits, known as voltage multipliers or charge pumps and based on the use of capacitors, which must be capable of withstanding the high voltages involved in the final stages of the circuit.
These capacitors can be formed between the polycrystalline silicon and a diffusion provided in the substrate, using the high voltage oxide as a dielectric. However, they have certain disadvantages, as follows:
the diffusion which forms one of the capacitor electrodes is part of the standard processing flow for EEPROMs, but involves an additional masking step for FLASH EEPROM memories; and
one of the capacitor electrodes is connected to the substrate via a diode, which introduces limitations on the supply polarities.
On the other hand, non-volatile memories of the EPROM, FLASH EEPROM and EEPROM types include two levels of polycrystalline silicon, separated by a dielectric, which lend themselves ideally for forming a capacitor with both electrodes floating.
A limiting factor to the use, in integrated circuits of this kind, of capacitors formed between two levels of polysilicon is represented by the maximum voltage that the interpoly oxide can withstand. This oxide is usually quite thin (within the range of 15 to 20 nm), since it has to be used in memory cells. In fact, the efficiency of the memory cell is critically dependent on the coupling coefficient between the control gate and the floating gate, which is the better the thinner the interpoly dielectric, whose lower limit is only set by problems of faulty construction. However, forming thick and thin interpoly dielectrics simultaneously in the same device is a fairly complicated operation involving at least one masking step.
The underlying technical problem of this invention is to enable the formation of a high voltage capacitor in a double polysilicon level, monolithically integratable on a semiconductor substrate without the addition of technological steps to the manufacturing process of the device to which the capacitor is integrated, thereby overcoming the aforementioned limitations of the prior art.
The technical problem is solved by a capacitor as further described below.
SUMMARY OF THE INVENTION
It is a primary objective of the present invention to provide a high voltage capacitor which is integratable monolithically on a semiconductor substrate which accommodates a field oxide region overlaid by a first layer of polycrystalline silicon isolated from a second layer of polycrystalline silicon by an interpoly dielectric layer, and comprises two elementary capacitors having a first common conductive plate which is formed in the first layer of polycrystalline silicon. Each of these elementary capacitors has a second conductive plate formed in the second layer of polycrystalline silicon above the first plate, and includes said interpoly dielectric layer as an isolation dielectric between the two plates.
Additional objects, advantages, and novel features of the present invention will become apparent to those skilled in the art from this disclosure, including the following detailed description, as well as by practice of the invention. While the invention is described below with reference to preferred embodiment(s), it should be understood that the invention is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the invention as disclosed and claimed herein and with respect to which the invention could be of significant utility.
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Nondestructive Readout 3 Dimensional Dual Insulator Memory,IBM Technical Disclosure Bulletin, vol. 17, No. 1, pp. 28-29, Jun. 1974.
Baldi Livio
Ghezzi Paolo
Maurelli Alfonso
Carroll J.
Galanthay Theodore E.
Jenkens & Gilchrist P.C.
SGS--Thomson Microelectronics S.r.l.
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