High tunability CMOS delay element

Details High tunability CMOS delay element High tunability CMOS delay element

1999-11-17

2001-07-03

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S274000, C327S287000

Reexamination Certificate

active

06255881

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to CMOS analog integrated circuits and in particular to a method for extending the tuning range of a delay element forming a part of such a circuit and destined to be used for the implementation of ring oscillators or of delay lock circuits. The invention relates also to the high tunability delay element so obtained.
BACKGROUND OF THE INVENTION
In the essence, a delay element is formed by an amplification element, in order not to attenuate the signal, and by a load reproducing the input voltage at its output. The delay depends on the time required by the amplifier to reproduce the input voltage on the load.
In the most common applications, a plurality of these elements is connected in cascade to form a controlled delay line or a ring oscillator. In the design of this type of device, utmost importance is devoted to the choice of the structure of the basic block that implements the delay and amplification. The most usual choice is to use structures based on differential amplifiers, since their use allows reducing the effects of the noises that add to the signal in a common mode due to capacitive couplings. Further, the element chosen must allow a variability of the delay introduced, to allow the implementation of tuneable delay lines or ring oscillators.
When facing the tunability issue, one has to overcome definitively the problem of the spread of the characteristics of the different specimen (i.e. the spread being due to variations in the process conditions for the implementation of the individual specimen), in addition to the extreme sensitivity of the components to operating conditions (power supply voltage and temperature). The device must therefore exhibit a high flexibility in order that all the requirements may be met as the operating and process conditions vary. In particular, the tunability range of the individual delay element shall have to ensure at least the achievement of a delay of interest (and therefore, in the case of a tuneable oscillator, of an oscillation frequency of interest), whatever the operating and process conditions might be.
So far various delay elements of differential structures have been suggested for achieving the above-cited targets.
The document “Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits—A Tutorial”, by B. Razavi, published on page 1 and ff. of the book “Monolithic phase-locked loops and clock recovery circuits—Theory and Design”, edited by B. Razavi and published by The Institute of Electrical and Electronics Engineers, Inc., New York (USA), 1996, discloses a CMOS circuit substantially consisting of a differential amplifier in which the gates of the load transistors are biased by respective source follower stages so as to compensate for the gate-source voltage drops of the transistors and allow the operation at the low voltage values commonly used in CMOS technology. The transistors of the source follower stages are biased by a constant current. The delay modulation is obtained by modulating the rest current that flows through a pair of N type transistors that introduce a local positive feedback and that, for the small signals involved, form each a negative impedance in parallel to the positive impedance of the load P type transistors. To guarantee the constancy of the oscillation amplitude, the rest current in the load transistors is kept constant, and this may be achieved by driving the current mirrors that supply the differential stage and the feedback stage in such a way as to obtain a constant sum of respective currents. The document states that the circuit, when used in an oscillator, has a tunability range of about an octave (i.e. a maximum frequency about twice the minimum frequency). This bound is set by the fact that the transconductance of the feedback transistors cannot exceed that of the load transistors, to ensure that the total impedance of the load (resulting from the parallel connection between the positive impedance of the load transistor and the negative impedance of the respective feedback transistor) will not become negative, thus making the circuit unstable.
A range of this size is insufficient by itself for the application in particular in oscillators to be used within integrated circuits, where a high flexibility is required (for instance oscillation frequencies ranging for instance from a hundred MHz to more than 1 GHz are to be achieved). Furthermore, it has been experienced in practice that the spread of the characteristics of the components due to the variations of the fabrication process and operating conditions causes fluctuations of the upper and lowers bounds of the tunability range of an amplitude comparable to the amplitude of the range itself, and this further reduces the range actually guaranteed.
SUMMARY OF THE INVENTION
According to the invention, there are provided a method of extending the tunability range of a CMOS delay element, based on a differential amplifier, and the delay element with an extended tunability range obtained through such a method.
The method of extending the tunability range of a CMOS delay element is based on a differential amplifier comprising load transistors that have a first type of doping and are associated with respective gate biasing transistors, connected in a source follower configuration and having a second type of doping and with feedback transistors, also having the second type of doping and forming a negative impedance in parallel to a positive impedance formed by each of the load transistors. The load transistors and the feedback transistors are biased by respective currents variable in opposite directions upon variation of the delay to be introduced. The transistors connected in source follower configurations are biased by a bias current that is also made to vary so as to cause decrease in the impedance of the load transistors, and the bias current of the load transistors is made to vary in such a way as to reach a maximum value higher than the maximum value of the bias currents of the feedback transistors, so that the sum of said biasd currents of the load transistors and of the feedback transistors increases in a substantially linear way as to be introduced decreases.
The CMOS delay element can comprise a differential amplifier in which a pair of load transistors having a first type of doping, are associated with respective gate biasing transistors, connected in a source follower configuration and having a second type of doping, and with feedback transistors that also have the second type of doping and form a negative impedance in parallel to a positive impedance represented by each of the load transistors. The load transistors and the feedback transistors are associated with respective generators of control voltages such as to allow flow through said transistors, respective bias currents which vary in order to achieve the variation of the delay to be introduced by the element. The transistors biasing the gates of the load transistors are also associated with a generator of control voltage arranged to cause flow in the bias transistors of a bias current which is variable and linearly increasing in order to reduce the positive impedance of the load transistors. Generators of control voltages for the load transistors and the feedback transistors are arranged to cause flow in such transistors of bias currents such that the bias current of the load transistors rise to a maximum value higher than the maximum value of the bias current of the feedback transistors so that the sum of the bias currents of the load transistors and feedback transistors increases in a substantially linear way as the delay to be introduced decreases.
A delay line for a ring oscillator or a delay lock circuit comprises a cascade of CMOS delay elements with high tunability ranges as described.


REFERENCES:
patent: 5714912 (1998-02-01), Fiedler et al.
patent: 5994939 (1999-11-01), Johnson et al.
patent: 6043719 (2000-03-01), Lin et al.
“Monolithic Phase-Locked Loops and Clock Recovery Circuits”, Theory and Design, B.Razavi, I

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